# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
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# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
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# mach(): all
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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dec_b:
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dec_b:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; dec.b Rd
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;; dec.b Rd
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dec.b r0h ; Decrement 8-bit reg by one
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dec.b r0h ; Decrement 8-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa4a5 r0 ; dec result: a4|a5
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test_h_gr16 0xa4a5 r0 ; dec result: a4|a5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5
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test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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dec_w_1:
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dec_w_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; dec.w #1, Rd
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;; dec.w #1, Rd
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dec.w #1, r0 ; Decrement 16-bit reg by one
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dec.w #1, r0 ; Decrement 16-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a4 r0 ; dec result: a5|a4
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test_h_gr16 0xa5a4 r0 ; dec result: a5|a4
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test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
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test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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dec_w_2:
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dec_w_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; dec.w #2, Rd
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;; dec.w #2, Rd
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dec.w #2, r0 ; Decrement 16-bit reg by two
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dec.w #2, r0 ; Decrement 16-bit reg by two
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a3 r0 ; dec result: a5|a3
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test_h_gr16 0xa5a3 r0 ; dec result: a5|a3
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test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
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test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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dec_l_1:
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dec_l_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; dec.l #1, eRd
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;; dec.l #1, eRd
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dec.l #1, er0 ; Decrement 32-bit reg by one
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dec.l #1, er0 ; Decrement 32-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
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test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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dec_l_2:
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dec_l_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; dec.l #2, eRd
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;; dec.l #2, eRd
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dec.l #2, er0 ; Decrement 32-bit reg by two
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dec.l #2, er0 ; Decrement 32-bit reg by two
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
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test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.endif
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.endif
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pass
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pass
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exit 0
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exit 0
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