# Hitachi H8 testcase 'exts.l, extu.l'
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# Hitachi H8 testcase 'exts.l, extu.l'
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# mach(): h8300h h8300s h8sx
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# mach(): h8300h h8300s h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.data
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.data
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.align 4
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.align 4
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pos: .long 0xffff0001
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pos: .long 0xffff0001
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neg: .long 0x00008000
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neg: .long 0x00008000
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pos2: .long 0xffffff01
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pos2: .long 0xffffff01
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neg2: .long 0x00000080
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neg2: .long 0x00000080
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.text
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.text
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exts_l_reg32_p:
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exts_l_reg32_p:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l ern32
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;; exts.l ern32
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mov.w #1, r0
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mov.w #1, r0
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exts.l er0
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exts.l er0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 0x00000001 er0 ; result of sign extend
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test_h_gr32 0x00000001 er0 ; result of sign extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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exts_l_reg32_n:
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exts_l_reg32_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l ern32
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;; exts.l ern32
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mov.w #0xffff, r0
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mov.w #0xffff, r0
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exts.l er0
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exts.l er0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_neg_set
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_carry_clear
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test_carry_clear
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test_h_gr32 0xffffffff er0 ; result of sign extend
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test_h_gr32 0xffffffff er0 ; result of sign extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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extu_l_reg32_n:
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extu_l_reg32_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; extu.l ern32
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;; extu.l ern32
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mov.w #0xffff, r0
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mov.w #0xffff, r0
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extu.l er0
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extu.l er0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 0x0000ffff er0 ; result of zero extend
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test_h_gr32 0x0000ffff er0 ; result of zero extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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exts_l_ind_p:
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exts_l_ind_p:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32
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;; exts.l @ern32
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mov.l #pos, er1
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mov.l #pos, er1
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exts.l @er1
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exts.l @er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 pos er1 ; er1 still contains target address
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test_h_gr32 pos er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00000001, @pos
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cmp.l #0x00000001, @pos
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beq .Lslindp
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beq .Lslindp
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fail
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fail
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.Lslindp:
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.Lslindp:
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mov.l #0xffff0001, @pos ; Restore initial value
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mov.l #0xffff0001, @pos ; Restore initial value
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exts_l_ind_n:
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exts_l_ind_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32
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;; exts.l @ern32
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mov.l #neg, er1
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mov.l #neg, er1
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exts.l @er1
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exts.l @er1
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_neg_set
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_carry_clear
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test_carry_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0xffff8000, @neg
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cmp.l #0xffff8000, @neg
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beq .Lslindn
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beq .Lslindn
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fail
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fail
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.Lslindn:
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.Lslindn:
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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extu_l_ind_n:
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extu_l_ind_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; extu.l @ern32
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;; extu.l @ern32
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mov.l #neg, er1
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mov.l #neg, er1
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extu.l @er1
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extu.l @er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00008000, @neg
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cmp.l #0x00008000, @neg
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beq .Lulindn
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beq .Lulindn
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fail
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fail
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.Lulindn:
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.Lulindn:
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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exts_l_postinc_p:
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exts_l_postinc_p:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32+
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;; exts.l @ern32+
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mov.l #pos, er1
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mov.l #pos, er1
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exts.l @er1+
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exts.l @er1+
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 pos+4 er1 ; er1 still contains target address
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test_h_gr32 pos+4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00000001, @pos
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cmp.l #0x00000001, @pos
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beq .Lslpostincp
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beq .Lslpostincp
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fail
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fail
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.Lslpostincp:
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.Lslpostincp:
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mov.l #0xffff0001, @pos ; Restore initial value
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mov.l #0xffff0001, @pos ; Restore initial value
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exts_l_postinc_n:
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exts_l_postinc_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32+
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;; exts.l @ern32+
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mov.l #neg, er1
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mov.l #neg, er1
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exts.l @er1+
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exts.l @er1+
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_neg_set
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_carry_clear
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test_carry_clear
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test_h_gr32 neg+4 er1 ; er1 still contains target address
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test_h_gr32 neg+4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0xffff8000, @neg
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cmp.l #0xffff8000, @neg
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beq .Lslpostincn
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beq .Lslpostincn
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fail
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fail
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.Lslpostincn:
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.Lslpostincn:
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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extu_l_postinc_n:
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extu_l_postinc_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; extu.l @ern32+
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;; extu.l @ern32+
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mov.l #neg, er1
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mov.l #neg, er1
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extu.l @er1+
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extu.l @er1+
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 neg+4 er1 ; er1 still contains target address
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test_h_gr32 neg+4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00008000, @neg
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cmp.l #0x00008000, @neg
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beq .Lulpostincn
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beq .Lulpostincn
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fail
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fail
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.Lulpostincn:
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.Lulpostincn:
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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exts_l_postdec_p:
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exts_l_postdec_p:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32-
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;; exts.l @ern32-
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mov.l #pos, er1
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mov.l #pos, er1
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exts.l @er1-
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exts.l @er1-
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 pos-4 er1 ; er1 still contains target address
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test_h_gr32 pos-4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00000001, @pos
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cmp.l #0x00000001, @pos
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beq .Lslpostdecp
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beq .Lslpostdecp
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fail
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fail
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.Lslpostdecp:
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.Lslpostdecp:
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mov.l #0xffff0001, @pos ; Restore initial value
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mov.l #0xffff0001, @pos ; Restore initial value
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exts_l_postdec_n:
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exts_l_postdec_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; exts.l @ern32-
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;; exts.l @ern32-
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mov.l #neg, er1
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mov.l #neg, er1
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exts.l @er1-
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exts.l @er1-
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_neg_set
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_carry_clear
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test_carry_clear
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test_h_gr32 neg-4 er1 ; er1 still contains target address
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test_h_gr32 neg-4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0xffff8000, @neg
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cmp.l #0xffff8000, @neg
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beq .Lslpostdecn
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beq .Lslpostdecn
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fail
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fail
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.Lslpostdecn:
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.Lslpostdecn:
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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;;; Note: leave the value as 0xffff8000, so that extu has work to do.
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extu_l_postdec_n:
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extu_l_postdec_n:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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;; extu.l @ern32-
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;; extu.l @ern32-
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mov.l #neg, er1
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mov.l #neg, er1
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extu.l @er1-
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extu.l @er1-
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_cc_clear
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test_h_gr32 neg-4 er1 ; er1 still contains target address
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test_h_gr32 neg-4 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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cmp.l #0x00008000, @neg
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cmp.l #0x00008000, @neg
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beq .Lulpostdecn
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beq .Lulpostdecn
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fail
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fail
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.Lulpostdecn:
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.Lulpostdecn:
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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;;; Note: leave the value as 0x00008000, so that extu has work to do.
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exts_l_preinc_p:
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exts_l_preinc_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l @+ern32
|
;; exts.l @+ern32
|
mov.l #pos-4, er1
|
mov.l #pos-4, er1
|
exts.l @+er1
|
exts.l @+er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos er1 ; er1 still contains target address
|
test_h_gr32 pos er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos
|
cmp.l #0x00000001, @pos
|
beq .Lslpreincp
|
beq .Lslpreincp
|
fail
|
fail
|
.Lslpreincp:
|
.Lslpreincp:
|
mov.l #0xffff0001, @pos ; Restore initial value
|
mov.l #0xffff0001, @pos ; Restore initial value
|
|
|
exts_l_preinc_n:
|
exts_l_preinc_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l @+ern32
|
;; exts.l @+ern32
|
mov.l #neg-4, er1
|
mov.l #neg-4, er1
|
exts.l @+er1
|
exts.l @+er1
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffff8000, @neg
|
cmp.l #0xffff8000, @neg
|
beq .Lslpreincn
|
beq .Lslpreincn
|
fail
|
fail
|
.Lslpreincn:
|
.Lslpreincn:
|
;;; Note: leave the value as 0xffff8000, so that extu has work to do.
|
;;; Note: leave the value as 0xffff8000, so that extu has work to do.
|
|
|
extu_l_preinc_n:
|
extu_l_preinc_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @+ern32
|
;; extu.l @+ern32
|
mov.l #neg-4, er1
|
mov.l #neg-4, er1
|
extu.l @+er1
|
extu.l @+er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Lulpreincn
|
beq .Lulpreincn
|
fail
|
fail
|
.Lulpreincn:
|
.Lulpreincn:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
exts_l_predec_p:
|
exts_l_predec_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l @-ern32
|
;; exts.l @-ern32
|
mov.l #pos+4, er1
|
mov.l #pos+4, er1
|
exts.l @-er1
|
exts.l @-er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos er1 ; er1 still contains target address
|
test_h_gr32 pos er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos
|
cmp.l #0x00000001, @pos
|
beq .Lslpredecp
|
beq .Lslpredecp
|
fail
|
fail
|
.Lslpredecp:
|
.Lslpredecp:
|
mov.l #0xffff0001, @pos ; Restore initial value
|
mov.l #0xffff0001, @pos ; Restore initial value
|
|
|
exts_l_predec_n:
|
exts_l_predec_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l @-ern32
|
;; exts.l @-ern32
|
mov.l #neg+4, er1
|
mov.l #neg+4, er1
|
exts.l @-er1
|
exts.l @-er1
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffff8000, @neg
|
cmp.l #0xffff8000, @neg
|
beq .Lslpredecn
|
beq .Lslpredecn
|
fail
|
fail
|
.Lslpredecn:
|
.Lslpredecn:
|
;;; Note: leave the value as 0xffff8000, so that extu has work to do.
|
;;; Note: leave the value as 0xffff8000, so that extu has work to do.
|
|
|
extu_l_predec_n:
|
extu_l_predec_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @-ern32
|
;; extu.l @-ern32
|
mov.l #neg+4, er1
|
mov.l #neg+4, er1
|
extu.l @-er1
|
extu.l @-er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_h_gr32 neg er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Lulpredecn
|
beq .Lulpredecn
|
fail
|
fail
|
.Lulpredecn:
|
.Lulpredecn:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
extu_l_disp2_n:
|
extu_l_disp2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @(dd:2, ern32)
|
;; extu.l @(dd:2, ern32)
|
mov.l #neg-8, er1
|
mov.l #neg-8, er1
|
extu.l @(8:2, er1)
|
extu.l @(8:2, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg-8 er1 ; er1 still contains target address
|
test_h_gr32 neg-8 er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Luldisp2n
|
beq .Luldisp2n
|
fail
|
fail
|
.Luldisp2n:
|
.Luldisp2n:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
extu_l_disp16_n:
|
extu_l_disp16_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @(dd:16, ern32)
|
;; extu.l @(dd:16, ern32)
|
mov.l #neg-44, er1
|
mov.l #neg-44, er1
|
extu.l @(44:16, er1)
|
extu.l @(44:16, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg-44 er1 ; er1 still contains target address
|
test_h_gr32 neg-44 er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Luldisp16n
|
beq .Luldisp16n
|
fail
|
fail
|
.Luldisp16n:
|
.Luldisp16n:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
extu_l_disp32_n:
|
extu_l_disp32_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @(dd:32, ern32)
|
;; extu.l @(dd:32, ern32)
|
mov.l #neg+444, er1
|
mov.l #neg+444, er1
|
extu.l @(-444:32, er1)
|
extu.l @(-444:32, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg+444 er1 ; er1 still contains target address
|
test_h_gr32 neg+444 er1 ; er1 still contains target address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Luldisp32n
|
beq .Luldisp32n
|
fail
|
fail
|
.Luldisp32n:
|
.Luldisp32n:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
extu_l_abs16_n:
|
extu_l_abs16_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @aa:16
|
;; extu.l @aa:16
|
extu.l @neg:16
|
extu.l @neg:16
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Lulabs16n
|
beq .Lulabs16n
|
fail
|
fail
|
.Lulabs16n:
|
.Lulabs16n:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
extu_l_abs32_n:
|
extu_l_abs32_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l @aa:32
|
;; extu.l @aa:32
|
extu.l @neg:32
|
extu.l @neg:32
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00008000, @neg
|
cmp.l #0x00008000, @neg
|
beq .Lulabs32n
|
beq .Lulabs32n
|
fail
|
fail
|
.Lulabs32n:
|
.Lulabs32n:
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
;;; Note: leave the value as 0x00008000, so that extu has work to do.
|
|
|
|
|
|
|
#
|
#
|
# exts #2, nn
|
# exts #2, nn
|
#
|
#
|
|
|
exts_l_reg32_2_p:
|
exts_l_reg32_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, ern32
|
;; exts.l #2, ern32
|
mov.b #1, r0l
|
mov.b #1, r0l
|
exts.l #2, er0
|
exts.l #2, er0
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 0x00000001 er0 ; result of sign extend
|
test_h_gr32 0x00000001 er0 ; result of sign extend
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
exts_l_reg32_2_n:
|
exts_l_reg32_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, ern32
|
;; exts.l #2, ern32
|
mov.b #0xff, r0l
|
mov.b #0xff, r0l
|
exts.l #2, er0
|
exts.l #2, er0
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 0xffffffff er0 ; result of sign extend
|
test_h_gr32 0xffffffff er0 ; result of sign extend
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
extu_l_reg32_2_n:
|
extu_l_reg32_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, ern32
|
;; extu.l #2, ern32
|
mov.b #0xff, r0l
|
mov.b #0xff, r0l
|
extu.l #2, er0
|
extu.l #2, er0
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 0x000000ff er0 ; result of zero extend
|
test_h_gr32 0x000000ff er0 ; result of zero extend
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
exts_l_ind_2_p:
|
exts_l_ind_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32
|
;; exts.l #2, @ern32
|
mov.l #pos2, er1
|
mov.l #pos2, er1
|
exts.l #2, @er1
|
exts.l #2, @er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos2
|
cmp.l #0x00000001, @pos2
|
beq .Lslindp2
|
beq .Lslindp2
|
fail
|
fail
|
.Lslindp2:
|
.Lslindp2:
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
|
|
exts_l_ind_2_n:
|
exts_l_ind_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32
|
;; exts.l #2, @ern32
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
exts.l #2, @er1
|
exts.l #2, @er1
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffffff80, @neg2
|
cmp.l #0xffffff80, @neg2
|
beq .Lslindn2
|
beq .Lslindn2
|
fail
|
fail
|
.Lslindn2:
|
.Lslindn2:
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
|
|
extu_l_ind_2_n:
|
extu_l_ind_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @ern32
|
;; extu.l #2, @ern32
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
extu.l #2, @er1
|
extu.l #2, @er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulindn2
|
beq .Lulindn2
|
fail
|
fail
|
.Lulindn2:
|
.Lulindn2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
exts_l_postinc_2_p:
|
exts_l_postinc_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32+
|
;; exts.l #2, @ern32+
|
mov.l #pos2, er1
|
mov.l #pos2, er1
|
exts.l #2, @er1+
|
exts.l #2, @er1+
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos2+4 er1 ; result of sign extend
|
test_h_gr32 pos2+4 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos2
|
cmp.l #0x00000001, @pos2
|
beq .Lslpostincp2
|
beq .Lslpostincp2
|
fail
|
fail
|
.Lslpostincp2:
|
.Lslpostincp2:
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
|
|
exts_l_postinc_2_n:
|
exts_l_postinc_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32+
|
;; exts.l #2, @ern32+
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
exts.l #2, @er1+
|
exts.l #2, @er1+
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg2+4 er1 ; result of sign extend
|
test_h_gr32 neg2+4 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffffff80, @neg2
|
cmp.l #0xffffff80, @neg2
|
beq .Lslpostincn2
|
beq .Lslpostincn2
|
fail
|
fail
|
.Lslpostincn2:
|
.Lslpostincn2:
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
|
|
extu_l_postinc_2_n:
|
extu_l_postinc_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @ern32+
|
;; extu.l #2, @ern32+
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
extu.l #2, @er1+
|
extu.l #2, @er1+
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2+4 er1 ; result of zero extend
|
test_h_gr32 neg2+4 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulpostincn2
|
beq .Lulpostincn2
|
fail
|
fail
|
.Lulpostincn2:
|
.Lulpostincn2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
exts_l_postdec_2_p:
|
exts_l_postdec_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32-
|
;; exts.l #2, @ern32-
|
mov.l #pos2, er1
|
mov.l #pos2, er1
|
exts.l #2, @er1-
|
exts.l #2, @er1-
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos2-4 er1 ; result of sign extend
|
test_h_gr32 pos2-4 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos2
|
cmp.l #0x00000001, @pos2
|
beq .Lslpostdecp2
|
beq .Lslpostdecp2
|
fail
|
fail
|
.Lslpostdecp2:
|
.Lslpostdecp2:
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
|
|
exts_l_postdec_2_n:
|
exts_l_postdec_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @ern32-
|
;; exts.l #2, @ern32-
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
exts.l #2, @er1-
|
exts.l #2, @er1-
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg2-4 er1 ; result of sign extend
|
test_h_gr32 neg2-4 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffffff80, @neg2
|
cmp.l #0xffffff80, @neg2
|
beq .Lslpostdecn2
|
beq .Lslpostdecn2
|
fail
|
fail
|
.Lslpostdecn2:
|
.Lslpostdecn2:
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
|
|
extu_l_postdec_2_n:
|
extu_l_postdec_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @ern32-
|
;; extu.l #2, @ern32-
|
mov.l #neg2, er1
|
mov.l #neg2, er1
|
extu.l #2, @er1-
|
extu.l #2, @er1-
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2-4 er1 ; result of zero extend
|
test_h_gr32 neg2-4 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulpostdecn2
|
beq .Lulpostdecn2
|
fail
|
fail
|
.Lulpostdecn2:
|
.Lulpostdecn2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
exts_l_preinc_2_p:
|
exts_l_preinc_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @+ern32
|
;; exts.l #2, @+ern32
|
mov.l #pos2-4, er1
|
mov.l #pos2-4, er1
|
exts.l #2, @+er1
|
exts.l #2, @+er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos2
|
cmp.l #0x00000001, @pos2
|
beq .Lslpreincp2
|
beq .Lslpreincp2
|
fail
|
fail
|
.Lslpreincp2:
|
.Lslpreincp2:
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
|
|
exts_l_preinc_2_n:
|
exts_l_preinc_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @+ern32
|
;; exts.l #2, @+ern32
|
mov.l #neg2-4, er1
|
mov.l #neg2-4, er1
|
exts.l #2, @+er1
|
exts.l #2, @+er1
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffffff80, @neg2
|
cmp.l #0xffffff80, @neg2
|
beq .Lslpreincn2
|
beq .Lslpreincn2
|
fail
|
fail
|
.Lslpreincn2:
|
.Lslpreincn2:
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
|
|
extu_l_preinc_2_n:
|
extu_l_preinc_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @+ern32
|
;; extu.l #2, @+ern32
|
mov.l #neg2-4, er1
|
mov.l #neg2-4, er1
|
extu.l #2, @+er1
|
extu.l #2, @+er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulpreincn2
|
beq .Lulpreincn2
|
fail
|
fail
|
.Lulpreincn2:
|
.Lulpreincn2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
exts_l_predec_2_p:
|
exts_l_predec_2_p:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @-ern32
|
;; exts.l #2, @-ern32
|
mov.l #pos2+4, er1
|
mov.l #pos2+4, er1
|
exts.l #2, @-er1
|
exts.l #2, @-er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_h_gr32 pos2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000001, @pos2
|
cmp.l #0x00000001, @pos2
|
beq .Lslpredecp2
|
beq .Lslpredecp2
|
fail
|
fail
|
.Lslpredecp2:
|
.Lslpredecp2:
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
mov.l #0xffffff01, @pos2 ; Restore initial value
|
|
|
exts_l_predec_2_n:
|
exts_l_predec_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; exts.l #2, @-ern32
|
;; exts.l #2, @-ern32
|
mov.l #neg2+4, er1
|
mov.l #neg2+4, er1
|
exts.l #2, @-er1
|
exts.l #2, @-er1
|
|
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
;; Test ccr H=0 N=1 Z=0 V=0 C=0
|
test_neg_set
|
test_neg_set
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_carry_clear
|
test_carry_clear
|
|
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_h_gr32 neg2 er1 ; result of sign extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0xffffff80, @neg2
|
cmp.l #0xffffff80, @neg2
|
beq .Lslpredecn2
|
beq .Lslpredecn2
|
fail
|
fail
|
.Lslpredecn2:
|
.Lslpredecn2:
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
;;; Note: leave the value as 0xffffff80, so that extu has work to do.
|
|
|
extu_l_predec_2_n:
|
extu_l_predec_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @-ern32
|
;; extu.l #2, @-ern32
|
mov.l #neg2+4, er1
|
mov.l #neg2+4, er1
|
extu.l #2, @-er1
|
extu.l #2, @-er1
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_h_gr32 neg2 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulpredecn2
|
beq .Lulpredecn2
|
fail
|
fail
|
.Lulpredecn2:
|
.Lulpredecn2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
extu_l_disp2_2_n:
|
extu_l_disp2_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @(dd:2, ern32)
|
;; extu.l #2, @(dd:2, ern32)
|
mov.l #neg2-8, er1
|
mov.l #neg2-8, er1
|
extu.l #2, @(8:2, er1)
|
extu.l #2, @(8:2, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2-8 er1 ; result of zero extend
|
test_h_gr32 neg2-8 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Luldisp2n2
|
beq .Luldisp2n2
|
fail
|
fail
|
.Luldisp2n2:
|
.Luldisp2n2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
extu_l_disp16_2_n:
|
extu_l_disp16_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @(dd:16, ern32)
|
;; extu.l #2, @(dd:16, ern32)
|
mov.l #neg2-44, er1
|
mov.l #neg2-44, er1
|
extu.l #2, @(44:16, er1)
|
extu.l #2, @(44:16, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2-44 er1 ; result of zero extend
|
test_h_gr32 neg2-44 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Luldisp16n2
|
beq .Luldisp16n2
|
fail
|
fail
|
.Luldisp16n2:
|
.Luldisp16n2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
extu_l_disp32_2_n:
|
extu_l_disp32_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @(dd:32, ern32)
|
;; extu.l #2, @(dd:32, ern32)
|
mov.l #neg2+444, er1
|
mov.l #neg2+444, er1
|
extu.l #2, @(-444:32, er1)
|
extu.l #2, @(-444:32, er1)
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_h_gr32 neg2+444 er1 ; result of zero extend
|
test_h_gr32 neg2+444 er1 ; result of zero extend
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Luldisp32n2
|
beq .Luldisp32n2
|
fail
|
fail
|
.Luldisp32n2:
|
.Luldisp32n2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
extu_l_abs16_2_n:
|
extu_l_abs16_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @aa:16
|
;; extu.l #2, @aa:16
|
extu.l #2, @neg2:16
|
extu.l #2, @neg2:16
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulabs16n2
|
beq .Lulabs16n2
|
fail
|
fail
|
.Lulabs16n2:
|
.Lulabs16n2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
extu_l_abs32_2_n:
|
extu_l_abs32_2_n:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
;; extu.l #2, @aa:32
|
;; extu.l #2, @aa:32
|
extu.l #2, @neg2:32
|
extu.l #2, @neg2:32
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
test_cc_clear
|
test_cc_clear
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
cmp.l #0x00000080, @neg2
|
cmp.l #0x00000080, @neg2
|
beq .Lulabs32n2
|
beq .Lulabs32n2
|
fail
|
fail
|
.Lulabs32n2:
|
.Lulabs32n2:
|
;;; Note: leave the value as 0x00000080, like it started out.
|
;;; Note: leave the value as 0x00000080, like it started out.
|
|
|
.endif
|
.endif
|
|
|
pass
|
pass
|
|
|
exit 0
|
exit 0
|
|
|
|
|
|
|
|
|
|
|
