# Hitachi H8 testcase 'movmd'
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# Hitachi H8 testcase 'movmd'
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# mach(): h8sx
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# mach(): h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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.data
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.data
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byte_src:
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byte_src:
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.byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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.byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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byte_dst:
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byte_dst:
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.align 2
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.align 2
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word_src:
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word_src:
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.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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word_dst:
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word_dst:
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.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.align 4
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.align 4
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long_src:
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long_src:
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.long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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.long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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long_dst:
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long_dst:
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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start
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start
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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movmd_b:#
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movmd_b:#
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# Byte block transfer
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# Byte block transfer
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#
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#
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set_grs_a5a5
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set_grs_a5a5
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mov #byte_src, er5
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mov #byte_src, er5
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mov #byte_dst, er6
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mov #byte_dst, er6
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mov #10, r4
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mov #10, r4
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set_ccr_zero
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set_ccr_zero
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;; movmd.b
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;; movmd.b
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movmd.b
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movmd.b
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;;; .word 0x7b94
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;;; .word 0x7b94
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test_cc_clear
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test_cc_clear
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test_gr_a5a5 0
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 byte_src+10 er5
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test_h_gr32 byte_src+10 er5
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test_h_gr32 byte_dst+10 er6
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test_h_gr32 byte_dst+10 er6
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test_gr_a5a5 7
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test_gr_a5a5 7
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#
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#
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# Now make sure exactly 10 bytes were transferred.
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# Now make sure exactly 10 bytes were transferred.
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memcmp byte_src byte_dst 10
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memcmp byte_src byte_dst 10
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cmp.b #0, @byte_dst+10
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cmp.b #0, @byte_dst+10
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beq .L0
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beq .L0
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fail
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fail
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.L0:
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.L0:
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movmd_w:#
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movmd_w:#
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# Word block transfer
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# Word block transfer
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#
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#
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set_grs_a5a5
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set_grs_a5a5
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mov #word_src, er5
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mov #word_src, er5
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mov #word_dst, er6
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mov #word_dst, er6
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mov #10, r4
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mov #10, r4
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set_ccr_zero
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set_ccr_zero
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;; movmd.w
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;; movmd.w
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movmd.w
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movmd.w
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;;; .word 0x7ba4
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;;; .word 0x7ba4
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test_cc_clear
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test_cc_clear
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test_gr_a5a5 0
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 word_src+20 er5
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test_h_gr32 word_src+20 er5
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test_h_gr32 word_dst+20 er6
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test_h_gr32 word_dst+20 er6
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test_gr_a5a5 7
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test_gr_a5a5 7
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#
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#
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# Now make sure exactly 20 bytes were transferred.
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# Now make sure exactly 20 bytes were transferred.
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memcmp word_src word_dst 20
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memcmp word_src word_dst 20
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cmp.w #0, @word_dst+20
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cmp.w #0, @word_dst+20
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beq .L1
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beq .L1
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fail
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fail
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.L1:
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.L1:
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movmd_l:#
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movmd_l:#
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# Long block transfer
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# Long block transfer
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#
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#
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set_grs_a5a5
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set_grs_a5a5
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mov #long_src, er5
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mov #long_src, er5
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mov #long_dst, er6
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mov #long_dst, er6
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mov #10, r4
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mov #10, r4
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set_ccr_zero
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set_ccr_zero
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;; movmd.b
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;; movmd.b
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movmd.l
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movmd.l
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;;; .word 0x7bb4
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;;; .word 0x7bb4
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test_cc_clear
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test_cc_clear
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test_gr_a5a5 0
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 0xa5a50000 er4
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test_h_gr32 long_src+40 er5
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test_h_gr32 long_src+40 er5
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test_h_gr32 long_dst+40 er6
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test_h_gr32 long_dst+40 er6
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test_gr_a5a5 7
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test_gr_a5a5 7
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#
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#
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# Now make sure exactly 40 bytes were transferred.
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# Now make sure exactly 40 bytes were transferred.
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memcmp long_src long_dst 40
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memcmp long_src long_dst 40
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cmp.l #0, @long_dst+40
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cmp.l #0, @long_dst+40
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beq .L2
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beq .L2
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fail
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fail
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.L2:
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.L2:
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.endif
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.endif
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pass
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pass
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exit 0
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exit 0
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