# Hitachi H8 testcase 'rotl'
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# Hitachi H8 testcase 'rotl'
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# mach(): all
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.data
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.data
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byte_dest: .byte 0xa5
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byte_dest: .byte 0xa5
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.align 2
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.align 2
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word_dest: .word 0xa5a5
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word_dest: .word 0xa5a5
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.align 4
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.align 4
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long_dest: .long 0xa5a5a5a5
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long_dest: .long 0xa5a5a5a5
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.text
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.text
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rotl_b_reg8_1:
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rotl_b_reg8_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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rotl.b r0l ; shift left arithmetic by one
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rotl.b r0l ; shift left arithmetic by one
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011
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test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011
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.if (sim_cpu)
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.if (sim_cpu)
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test_h_gr32 0xa5a5a54b er0
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test_h_gr32 0xa5a5a54b er0
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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rotl_b_ind_1:
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rotl_b_ind_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest, er0
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mov #byte_dest, er0
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rotl.b @er0 ; shift right arithmetic by one, indirect
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rotl.b @er0 ; shift right arithmetic by one, indirect
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 byte_dest er0
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test_h_gr32 byte_dest er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbind1
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beq .Lbind1
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fail
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fail
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.Lbind1:
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.Lbind1:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexb16_1:
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rotl_b_indexb16_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.b #5, r0l
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mov.b #5, r0l
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rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte
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rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xa5a5a505 er0
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test_h_gr32 0xa5a5a505 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexb161
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beq .Lbindexb161
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fail
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fail
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.Lbindexb161:
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.Lbindexb161:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexw16_1:
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rotl_b_indexw16_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.w #256, r0
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mov.w #256, r0
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rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word
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rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xa5a50100 er0
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test_h_gr32 0xa5a50100 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexw161
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beq .Lbindexw161
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fail
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fail
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.Lbindexw161:
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.Lbindexw161:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexl16_1:
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rotl_b_indexl16_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.l #0xffffffff, er0
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mov.l #0xffffffff, er0
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rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long
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rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xffffffff er0
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test_h_gr32 0xffffffff er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexl161
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beq .Lbindexl161
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fail
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fail
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.Lbindexl161:
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.Lbindexl161:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexb32_1:
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rotl_b_indexb32_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.b #5, r1l
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mov.b #5, r1l
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rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte
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rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xa5a5a505 er1
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test_h_gr32 0xa5a5a505 er1
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexb321
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beq .Lbindexb321
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fail
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fail
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.Lbindexb321:
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.Lbindexb321:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexw32_1:
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rotl_b_indexw32_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.w #256, r1
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mov.w #256, r1
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rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word
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rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xa5a50100 er1
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test_h_gr32 0xa5a50100 er1
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexw321
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beq .Lbindexw321
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fail
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fail
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.Lbindexw321:
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.Lbindexw321:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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rotl_b_indexl32_1:
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rotl_b_indexl32_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov.l #0xffffffff, er1
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mov.l #0xffffffff, er1
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rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long
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rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 0xffffffff er1
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test_h_gr32 0xffffffff er1
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 0100 1011
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; 1010 0101 -> 0100 1011
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cmp.b #0x4b, @byte_dest
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cmp.b #0x4b, @byte_dest
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beq .Lbindexl321
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beq .Lbindexl321
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fail
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fail
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.Lbindexl321:
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.Lbindexl321:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
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.endif
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.endif
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rotl_b_reg8_2:
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rotl_b_reg8_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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rotl.b #2, r0l ; shift left arithmetic by two
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rotl.b #2, r0l ; shift left arithmetic by two
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110
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test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110
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.if (sim_cpu)
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.if (sim_cpu)
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test_h_gr32 0xa5a5a596 er0
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test_h_gr32 0xa5a5a596 er0
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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rotl_b_ind_2:
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rotl_b_ind_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest, er0
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mov #byte_dest, er0
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rotl.b #2, @er0 ; shift right arithmetic by one, indirect
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rotl.b #2, @er0 ; shift right arithmetic by one, indirect
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|
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test_carry_clear ; H=0 N=1 Z=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
|
|
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test_h_gr32 byte_dest er0
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test_h_gr32 byte_dest er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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; 1010 0101 -> 1001 0110
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; 1010 0101 -> 1001 0110
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cmp.b #0x96, @byte_dest
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cmp.b #0x96, @byte_dest
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beq .Lbind2
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beq .Lbind2
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fail
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fail
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.Lbind2:
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.Lbind2:
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mov.b #0xa5, @byte_dest
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mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexb16_2:
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rotl_b_indexb16_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
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mov.b #5, r0l
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mov.b #5, r0l
|
rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte
|
rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte
|
|
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test_carry_clear ; H=0 N=1 Z=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
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test_h_gr32 0xa5a5a505 er0
|
test_h_gr32 0xa5a5a505 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexb162
|
beq .Lbindexb162
|
fail
|
fail
|
.Lbindexb162:
|
.Lbindexb162:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexw16_2:
|
rotl_b_indexw16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r0
|
mov.w #256, r0
|
rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word
|
rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word
|
|
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er0
|
test_h_gr32 0xa5a50100 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexw162
|
beq .Lbindexw162
|
fail
|
fail
|
.Lbindexw162:
|
.Lbindexw162:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexl16_2:
|
rotl_b_indexl16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er0
|
mov.l #0xffffffff, er0
|
rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long
|
rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long
|
|
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er0
|
test_h_gr32 0xffffffff er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexl162
|
beq .Lbindexl162
|
fail
|
fail
|
.Lbindexl162:
|
.Lbindexl162:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexb32_2:
|
rotl_b_indexb32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r1l
|
mov.b #5, r1l
|
rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte
|
rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexb322
|
beq .Lbindexb322
|
fail
|
fail
|
.Lbindexb322:
|
.Lbindexb322:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexw32_2:
|
rotl_b_indexw32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r1
|
mov.w #256, r1
|
rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word
|
rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word
|
|
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er1
|
test_h_gr32 0xa5a50100 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexw322
|
beq .Lbindexw322
|
fail
|
fail
|
.Lbindexw322:
|
.Lbindexw322:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
rotl_b_indexl32_2:
|
rotl_b_indexl32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er1
|
mov.l #0xffffffff, er1
|
rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long
|
rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long
|
|
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er1
|
test_h_gr32 0xffffffff er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 -> 1001 0110
|
; 1010 0101 -> 1001 0110
|
cmp.b #0x96, @byte_dest
|
cmp.b #0x96, @byte_dest
|
beq .Lbindexl322
|
beq .Lbindexl322
|
fail
|
fail
|
.Lbindexl322:
|
.Lbindexl322:
|
mov.b #0xa5, @byte_dest
|
mov.b #0xa5, @byte_dest
|
|
|
.endif
|
.endif
|
|
|
.if (sim_cpu) ; Not available in h8300 mode
|
.if (sim_cpu) ; Not available in h8300 mode
|
rotl_w_reg16_1:
|
rotl_w_reg16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
rotl.w r0 ; shift left arithmetic by one
|
rotl.w r0 ; shift left arithmetic by one
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
test_h_gr32 0xa5a54b4b er0
|
test_h_gr32 0xa5a54b4b er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
rotl_w_indexb16_1:
|
rotl_w_indexb16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r0l
|
mov.b #5, r0l
|
rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte
|
rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a5a505 er0
|
test_h_gr32 0xa5a5a505 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexb161
|
beq .Lwindexb161
|
fail
|
fail
|
.Lwindexb161:
|
.Lwindexb161:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexw16_1:
|
rotl_w_indexw16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r0
|
mov.w #256, r0
|
rotl.w @(word_dest-512:16, r0.w) ; indexed word/word
|
rotl.w @(word_dest-512:16, r0.w) ; indexed word/word
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a50100 er0
|
test_h_gr32 0xa5a50100 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexw161
|
beq .Lwindexw161
|
fail
|
fail
|
.Lwindexw161:
|
.Lwindexw161:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexl16_1:
|
rotl_w_indexl16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er0
|
mov.l #0xffffffff, er0
|
rotl.w @(word_dest+2:16, er0.l) ; indexed word/long
|
rotl.w @(word_dest+2:16, er0.l) ; indexed word/long
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xffffffff er0
|
test_h_gr32 0xffffffff er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexl161
|
beq .Lwindexl161
|
fail
|
fail
|
.Lwindexl161:
|
.Lwindexl161:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexb32_1:
|
rotl_w_indexb32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r1l
|
mov.b #5, r1l
|
rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte
|
rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexb321
|
beq .Lwindexb321
|
fail
|
fail
|
.Lwindexb321:
|
.Lwindexb321:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexw32_1:
|
rotl_w_indexw32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r1
|
mov.w #256, r1
|
rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte
|
rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a50100 er1
|
test_h_gr32 0xa5a50100 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexw321
|
beq .Lwindexw321
|
fail
|
fail
|
.Lwindexw321:
|
.Lwindexw321:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexl32_1:
|
rotl_w_indexl32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er1
|
mov.l #0xffffffff, er1
|
rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte
|
rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xffffffff er1
|
test_h_gr32 0xffffffff er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
; 1010 0101 1010 0101 -> 0100 1011 0100 1011
|
cmp.w #0x4b4b, @word_dest
|
cmp.w #0x4b4b, @word_dest
|
beq .Lwindexl321
|
beq .Lwindexl321
|
fail
|
fail
|
.Lwindexl321:
|
.Lwindexl321:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
.endif
|
.endif
|
|
|
rotl_w_reg16_2:
|
rotl_w_reg16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
rotl.w #2, r0 ; shift left arithmetic by two
|
rotl.w #2, r0 ; shift left arithmetic by two
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
test_h_gr32 0xa5a59696 er0
|
test_h_gr32 0xa5a59696 er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
rotl_w_indexb16_2:
|
rotl_w_indexb16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r0l
|
mov.b #5, r0l
|
rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte
|
rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a5a505 er0
|
test_h_gr32 0xa5a5a505 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexb162
|
beq .Lwindexb162
|
fail
|
fail
|
.Lwindexb162:
|
.Lwindexb162:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexw16_2:
|
rotl_w_indexw16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r0
|
mov.w #256, r0
|
rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word
|
rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er0
|
test_h_gr32 0xa5a50100 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexw162
|
beq .Lwindexw162
|
fail
|
fail
|
.Lwindexw162:
|
.Lwindexw162:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexl16_2:
|
rotl_w_indexl16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er0
|
mov.l #0xffffffff, er0
|
rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long
|
rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er0
|
test_h_gr32 0xffffffff er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexl162
|
beq .Lwindexl162
|
fail
|
fail
|
.Lwindexl162:
|
.Lwindexl162:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexb32_2:
|
rotl_w_indexb32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r1l
|
mov.b #5, r1l
|
rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte
|
rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexb322
|
beq .Lwindexb322
|
fail
|
fail
|
.Lwindexb322:
|
.Lwindexb322:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexw32_2:
|
rotl_w_indexw32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r1
|
mov.w #256, r1
|
rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte
|
rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er1
|
test_h_gr32 0xa5a50100 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexw322
|
beq .Lwindexw322
|
fail
|
fail
|
.Lwindexw322:
|
.Lwindexw322:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
|
|
rotl_w_indexl32_2:
|
rotl_w_indexl32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er1
|
mov.l #0xffffffff, er1
|
rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte
|
rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er1
|
test_h_gr32 0xffffffff er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
; 1010 0101 1010 0101 -> 1001 0110 1001 0110
|
cmp.w #0x9696, @word_dest
|
cmp.w #0x9696, @word_dest
|
beq .Lwindexl322
|
beq .Lwindexl322
|
fail
|
fail
|
.Lwindexl322:
|
.Lwindexl322:
|
mov.w #0xa5a5, @word_dest
|
mov.w #0xa5a5, @word_dest
|
.endif
|
.endif
|
|
|
rotl_l_reg32_1:
|
rotl_l_reg32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
rotl.l er0 ; shift left arithmetic by one
|
rotl.l er0 ; shift left arithmetic by one
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
test_h_gr32 0x4b4b4b4b er0
|
test_h_gr32 0x4b4b4b4b er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
rotl_l_indexb16_1:
|
rotl_l_indexb16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r0l
|
mov.b #5, r0l
|
rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte
|
rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a5a505 er0
|
test_h_gr32 0xa5a5a505 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexb161
|
beq .Llindexb161
|
fail
|
fail
|
.Llindexb161:
|
.Llindexb161:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexw16_1:
|
rotl_l_indexw16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r0
|
mov.w #256, r0
|
rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word
|
rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a50100 er0
|
test_h_gr32 0xa5a50100 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexw161
|
beq .Llindexw161
|
fail
|
fail
|
.Llindexw161:
|
.Llindexw161:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexl16_1:
|
rotl_l_indexl16_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er0
|
mov.l #0xffffffff, er0
|
rotl.l @(long_dest+4:16, er0.l) ; indexed long/long
|
rotl.l @(long_dest+4:16, er0.l) ; indexed long/long
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xffffffff er0
|
test_h_gr32 0xffffffff er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexl161
|
beq .Llindexl161
|
fail
|
fail
|
.Llindexl161:
|
.Llindexl161:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexb32_1:
|
rotl_l_indexb32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r1l
|
mov.b #5, r1l
|
rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte
|
rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexb321
|
beq .Llindexb321
|
fail
|
fail
|
.Llindexb321:
|
.Llindexb321:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexw32_1:
|
rotl_l_indexw32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r1
|
mov.w #256, r1
|
rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte
|
rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xa5a50100 er1
|
test_h_gr32 0xa5a50100 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexw321
|
beq .Llindexw321
|
fail
|
fail
|
.Llindexw321:
|
.Llindexw321:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexl32_1:
|
rotl_l_indexl32_1:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er1
|
mov.l #0xffffffff, er1
|
rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte
|
rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
test_h_gr32 0xffffffff er1
|
test_h_gr32 0xffffffff er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
; -> 0100 1011 0100 1011 0100 1011 0100 1011
|
cmp.l #0x4b4b4b4b, @long_dest
|
cmp.l #0x4b4b4b4b, @long_dest
|
beq .Llindexl321
|
beq .Llindexl321
|
fail
|
fail
|
.Llindexl321:
|
.Llindexl321:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
.endif
|
.endif
|
|
|
rotl_l_reg32_2:
|
rotl_l_reg32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
rotl.l #2, er0 ; shift left arithmetic by two
|
rotl.l #2, er0 ; shift left arithmetic by two
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
test_h_gr32 0x96969696 er0
|
test_h_gr32 0x96969696 er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
rotl_l_indexb16_2:
|
rotl_l_indexb16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r0l
|
mov.b #5, r0l
|
rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte
|
rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a5a505 er0
|
test_h_gr32 0xa5a5a505 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexb162
|
beq .Llindexb162
|
fail
|
fail
|
.Llindexb162:
|
.Llindexb162:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexw16_2:
|
rotl_l_indexw16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r0
|
mov.w #256, r0
|
rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word
|
rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er0
|
test_h_gr32 0xa5a50100 er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexw162
|
beq .Llindexw162
|
fail
|
fail
|
.Llindexw162:
|
.Llindexw162:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexl16_2:
|
rotl_l_indexl16_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er0
|
mov.l #0xffffffff, er0
|
rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long
|
rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er0
|
test_h_gr32 0xffffffff er0
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexl162
|
beq .Llindexl162
|
fail
|
fail
|
.Llindexl162:
|
.Llindexl162:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexb32_2:
|
rotl_l_indexb32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.b #5, r1l
|
mov.b #5, r1l
|
rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte
|
rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexb322
|
beq .Llindexb322
|
fail
|
fail
|
.Llindexb322:
|
.Llindexb322:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexw32_2:
|
rotl_l_indexw32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.w #256, r1
|
mov.w #256, r1
|
rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
|
rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xa5a50100 er1
|
test_h_gr32 0xa5a50100 er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexw322
|
beq .Llindexw322
|
fail
|
fail
|
.Llindexw322:
|
.Llindexw322:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
|
|
rotl_l_indexl32_2:
|
rotl_l_indexl32_2:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov.l #0xffffffff, er1
|
mov.l #0xffffffff, er1
|
rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte
|
rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
|
|
test_h_gr32 0xffffffff er1
|
test_h_gr32 0xffffffff er1
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
; -> 1001 0110 1001 0110 1001 0110 1001 0110
|
cmp.l #0x96969696, @long_dest
|
cmp.l #0x96969696, @long_dest
|
beq .Llindexl322
|
beq .Llindexl322
|
fail
|
fail
|
.Llindexl322:
|
.Llindexl322:
|
mov.l #0xa5a5a5a5, @long_dest
|
mov.l #0xa5a5a5a5, @long_dest
|
.endif
|
.endif
|
.endif
|
.endif
|
|
|
pass
|
pass
|
|
|
exit 0
|
exit 0
|
|
|
|
|
