OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [m32r/] [addv3.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# m32r testcase for addv3 $dr,$sr,#$simm16
# m32r testcase for addv3 $dr,$sr,#$simm16
# mach(): m32r m32rx
# mach(): m32r m32rx
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global addv3
        .global addv3
addv3:
addv3:
        mvi_h_condbit 0
        mvi_h_condbit 0
        mvi_h_gr r4, 1
        mvi_h_gr r4, 1
        mvi_h_gr r5, 1
        mvi_h_gr r5, 1
        addv3 r4, r5, #2
        addv3 r4, r5, #2
        bc not_ok
        bc not_ok
        test_h_gr r4, 3
        test_h_gr r4, 3
        mvi_h_gr r5, 0x7fff8001
        mvi_h_gr r5, 0x7fff8001
        addv3 r4, r5, #0x7fff
        addv3 r4, r5, #0x7fff
        bnc not_ok
        bnc not_ok
        pass
        pass
not_ok:
not_ok:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.