# m32r testcase for trap #$uimm4
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# m32r testcase for trap #$uimm4
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# mach(): m32r m32rx
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# mach(): m32r m32rx
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global trap
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.global trap
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trap:
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trap:
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; Test 1: bbpsw = 0, bpsw = 1, psw = 0
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; Test 1: bbpsw = 0, bpsw = 1, psw = 0
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; bbsm = 0, bie = 0, bbcond = 0
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; bbsm = 0, bie = 0, bbcond = 0
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvtc r4, cr8
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mvtc r4, cr8
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; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
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; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
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mvi_h_gr r4, 0xc100
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mvi_h_gr r4, 0xc100
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mvtc r4, cr0
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mvtc r4, cr0
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; bbpc = 0
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; bbpc = 0
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mvaddr_h_gr r4, 0
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mvaddr_h_gr r4, 0
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mvtc r4, bbpc
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mvtc r4, bbpc
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; bpc = 42
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; bpc = 42
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mvaddr_h_gr r4, 42
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mvaddr_h_gr r4, 42
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mvtc r4, bpc
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mvtc r4, bpc
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; Copy trap2_handler to trap area of memory.
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; Copy trap2_handler to trap area of memory.
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ld24 r0,#0x48 ; address of trap 2 handler
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ld24 r0,#0x48 ; address of trap 2 handler
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ld24 r1,#trap2_handler
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ld24 r1,#trap2_handler
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ld r2,@r1
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ld r2,@r1
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st r2,@r0
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st r2,@r0
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; Set up return address.
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; Set up return address.
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ld24 r5,#trap2_ret1
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ld24 r5,#trap2_ret1
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trap_insn1:
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trap_insn1:
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trap #2
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trap #2
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fail
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fail
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trap2_ret1:
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trap2_ret1:
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; test bbsm = 1, bbie = 1, bbcond = 1
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; test bbsm = 1, bbie = 1, bbcond = 1
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mvfc r4, cr8
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mvfc r4, cr8
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test_h_gr r4, 0xc1
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test_h_gr r4, 0xc1
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; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0
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; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0
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mvfc r4, cr0
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mvfc r4, cr0
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test_h_gr r4, 0
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test_h_gr r4, 0
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; test bbpc = 42
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; test bbpc = 42
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mvfc r4, bbpc
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mvfc r4, bbpc
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test_h_gr r4, 42
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test_h_gr r4, 42
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; test bpc = proper return address
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; test bpc = proper return address
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mvfc r4, bpc
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mvfc r4, bpc
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test_h_gr r4, trap_insn1 + 4
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test_h_gr r4, trap_insn1 + 4
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; Test 2: bbpsw = 1, bpsw = 0, psw = 1
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; Test 2: bbpsw = 1, bpsw = 0, psw = 1
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; bbsm = 1, bie = 1, bbcond = 1
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; bbsm = 1, bie = 1, bbcond = 1
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mvi_h_gr r4, 0xc1
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mvi_h_gr r4, 0xc1
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mvtc r4, cr8
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mvtc r4, cr8
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; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
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; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
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mvi_h_gr r4, 0xc1
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mvi_h_gr r4, 0xc1
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mvtc r4, cr0
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mvtc r4, cr0
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; bbpc = 42
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; bbpc = 42
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mvaddr_h_gr r4, 42
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mvaddr_h_gr r4, 42
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mvtc r4, bbpc
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mvtc r4, bbpc
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; bpc = 0
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; bpc = 0
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mvaddr_h_gr r4, 0
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mvaddr_h_gr r4, 0
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mvtc r4, bpc
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mvtc r4, bpc
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; Set up return address.
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; Set up return address.
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ld24 r5,#trap2_ret2
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ld24 r5,#trap2_ret2
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trap_insn2:
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trap_insn2:
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trap #2
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trap #2
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fail
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fail
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trap2_ret2:
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trap2_ret2:
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; test bbsm = 0, bbie = 0, bbcond = 0
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; test bbsm = 0, bbie = 0, bbcond = 0
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mvfc r4, cr8
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mvfc r4, cr8
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test_h_gr r4, 0
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test_h_gr r4, 0
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; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0
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; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0
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mvfc r4, cr0
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mvfc r4, cr0
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test_h_gr r4, 0xc180
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test_h_gr r4, 0xc180
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; test bbpc = 0
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; test bbpc = 0
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mvfc r4, bbpc
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mvfc r4, bbpc
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test_h_gr r4, 0
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test_h_gr r4, 0
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; test bpc = proper return address
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; test bpc = proper return address
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mvfc r4, bpc
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mvfc r4, bpc
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test_h_gr r4, trap_insn2 + 4
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test_h_gr r4, trap_insn2 + 4
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pass
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pass
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.data
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.data
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; Don't use rte as it will undo the effects of trap we're testing.
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; Don't use rte as it will undo the effects of trap we're testing.
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.p2align 2
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.p2align 2
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trap2_handler:
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trap2_handler:
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jmp r5
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jmp r5
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nop
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nop
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