URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [m32r/] [unlock.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# m32r testcase for unlock $src1,@$src2`	`# m32r testcase for unlock $src1,@$src2`
`# mach(): m32r m32rx`	`# mach(): m32r m32rx`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global unlock`	`.global unlock`
`unlock:`	`unlock:`
`mvaddr_h_gr r4, data_loc`	`mvaddr_h_gr r4, data_loc`
`mvi_h_gr r5, 1`	`mvi_h_gr r5, 1`

`lock r5, @r4`	`lock r5, @r4`

`mvi_h_gr r5, 2`	`mvi_h_gr r5, 2`
`unlock r5, @r4`	`unlock r5, @r4`

`ld r6, @r4`	`ld r6, @r4`
`test_h_gr r6, 2`	`test_h_gr r6, 2`

`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`
`unlock r5, @r4 ; This should be a nop since the processor should be unlocked.`	`unlock r5, @r4 ; This should be a nop since the processor should be unlocked.`

`ld r6, @r4`	`ld r6, @r4`
`test_h_gr r6, 2`	`test_h_gr r6, 2`

`pass`	`pass`

`data_loc:`	`data_loc:`
`.word 0`	`.word 0`