OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [m32r/] [uwrite32.ms] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# mach: m32r m32rx
# mach: m32r m32rx
# xerror:
# xerror:
# output: *misaligned write*
# output: *misaligned write*
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
; construct bra trap2_handler in trap 2 slot
; construct bra trap2_handler in trap 2 slot
        ld24 r0,#foo+1
        ld24 r0,#foo+1
        st r0,@r0
        st r0,@r0
        fail
        fail
        exit 0
        exit 0
.data
.data
        .p2align 2
        .p2align 2
foo:
foo:
        .word 42
        .word 42
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.