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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# sh testcase for bst
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# sh testcase for bst
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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.align 2
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.align 2
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_x: .long 0
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_x: .long 0
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_y: .long 0x55555555
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_y: .long 0x55555555
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start
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start
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bst_b_imm_disp12_reg:
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bst_b_imm_disp12_reg:
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set_grs_a5a5
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set_grs_a5a5
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# Make sure T is true to start.
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# Make sure T is true to start.
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sett
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sett
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mov.l x, r1
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mov.l x, r1
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bst.b #0, @(3, r1)
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bst.b #0, @(3, r1)
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assertmem _x, 0x1
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assertmem _x, 0x1
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bst.b #1, @(3, r1)
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bst.b #1, @(3, r1)
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assertmem _x, 0x3
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assertmem _x, 0x3
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bst.b #2, @(3, r1)
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bst.b #2, @(3, r1)
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assertmem _x, 0x7
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assertmem _x, 0x7
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bst.b #3, @(3, r1)
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bst.b #3, @(3, r1)
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assertmem _x, 0xf
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assertmem _x, 0xf
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bst.b #4, @(3, r1)
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bst.b #4, @(3, r1)
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assertmem _x, 0x1f
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assertmem _x, 0x1f
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bst.b #5, @(3, r1)
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bst.b #5, @(3, r1)
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assertmem _x, 0x3f
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assertmem _x, 0x3f
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bst.b #6, @(3, r1)
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bst.b #6, @(3, r1)
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assertmem _x, 0x7f
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assertmem _x, 0x7f
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bst.b #7, @(3, r1)
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bst.b #7, @(3, r1)
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assertmem _x, 0xff
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assertmem _x, 0xff
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bst.b #0, @(2, r1)
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bst.b #0, @(2, r1)
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assertmem _x, 0x1ff
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assertmem _x, 0x1ff
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bst.b #1, @(2, r1)
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bst.b #1, @(2, r1)
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assertmem _x, 0x3ff
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assertmem _x, 0x3ff
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bst.b #2, @(2, r1)
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bst.b #2, @(2, r1)
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assertmem _x, 0x7ff
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assertmem _x, 0x7ff
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bst.b #3, @(2, r1)
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bst.b #3, @(2, r1)
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assertmem _x, 0xfff
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assertmem _x, 0xfff
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bra .L2
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bra .L2
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nop
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nop
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.align 2
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.align 2
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x: .long _x
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x: .long _x
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y: .long _y
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y: .long _y
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.L2:
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.L2:
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bst.b #4, @(2, r1)
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bst.b #4, @(2, r1)
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assertmem _x, 0x1fff
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assertmem _x, 0x1fff
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bst.b #5, @(2, r1)
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bst.b #5, @(2, r1)
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assertmem _x, 0x3fff
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assertmem _x, 0x3fff
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bst.b #6, @(2, r1)
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bst.b #6, @(2, r1)
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assertmem _x, 0x7fff
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assertmem _x, 0x7fff
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bst.b #7, @(2, r1)
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bst.b #7, @(2, r1)
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assertmem _x, 0xffff
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assertmem _x, 0xffff
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bst.b #0, @(1, r1)
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bst.b #0, @(1, r1)
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assertmem _x, 0x1ffff
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assertmem _x, 0x1ffff
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bst.b #1, @(1, r1)
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bst.b #1, @(1, r1)
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assertmem _x, 0x3ffff
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assertmem _x, 0x3ffff
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bst.b #2, @(1, r1)
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bst.b #2, @(1, r1)
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assertmem _x, 0x7ffff
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assertmem _x, 0x7ffff
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bst.b #3, @(1, r1)
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bst.b #3, @(1, r1)
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assertmem _x, 0xfffff
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assertmem _x, 0xfffff
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bst.b #4, @(1, r1)
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bst.b #4, @(1, r1)
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assertmem _x, 0x1fffff
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assertmem _x, 0x1fffff
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bst.b #5, @(1, r1)
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bst.b #5, @(1, r1)
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assertmem _x, 0x3fffff
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assertmem _x, 0x3fffff
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bst.b #6, @(1, r1)
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bst.b #6, @(1, r1)
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assertmem _x, 0x7fffff
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assertmem _x, 0x7fffff
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bst.b #7, @(1, r1)
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bst.b #7, @(1, r1)
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assertmem _x, 0xffffff
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assertmem _x, 0xffffff
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bst.b #0, @(0, r1)
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bst.b #0, @(0, r1)
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assertmem _x, 0x1ffffff
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assertmem _x, 0x1ffffff
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bst.b #1, @(0, r1)
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bst.b #1, @(0, r1)
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assertmem _x, 0x3ffffff
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assertmem _x, 0x3ffffff
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bst.b #2, @(0, r1)
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bst.b #2, @(0, r1)
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assertmem _x, 0x7ffffff
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assertmem _x, 0x7ffffff
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bst.b #3, @(0, r1)
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bst.b #3, @(0, r1)
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assertmem _x, 0xfffffff
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assertmem _x, 0xfffffff
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bst.b #4, @(0, r1)
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bst.b #4, @(0, r1)
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assertmem _x, 0x1fffffff
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assertmem _x, 0x1fffffff
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bst.b #5, @(0, r1)
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bst.b #5, @(0, r1)
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assertmem _x, 0x3fffffff
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assertmem _x, 0x3fffffff
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bst.b #6, @(0, r1)
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bst.b #6, @(0, r1)
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assertmem _x, 0x7fffffff
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assertmem _x, 0x7fffffff
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bst.b #7, @(0, r1)
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bst.b #7, @(0, r1)
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assertmem _x, 0xffffffff
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assertmem _x, 0xffffffff
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assertreg _x, r1
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assertreg _x, r1
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bst_imm_reg:
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bst_imm_reg:
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set_greg 0, r1
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set_greg 0, r1
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bst #0, r1
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bst #0, r1
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assertreg 0x1, r1
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assertreg 0x1, r1
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bst #1, r1
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bst #1, r1
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assertreg 0x3, r1
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assertreg 0x3, r1
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bst #2, r1
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bst #2, r1
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assertreg 0x7, r1
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assertreg 0x7, r1
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bst #3, r1
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bst #3, r1
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assertreg 0xf, r1
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assertreg 0xf, r1
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bst #4, r1
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bst #4, r1
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assertreg 0x1f, r1
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assertreg 0x1f, r1
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bst #5, r1
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bst #5, r1
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assertreg 0x3f, r1
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assertreg 0x3f, r1
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bst #6, r1
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bst #6, r1
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assertreg 0x7f, r1
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assertreg 0x7f, r1
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bst #7, r1
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bst #7, r1
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assertreg 0xff, r1
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assertreg 0xff, r1
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test_gr_a5a5 r0
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test_gr_a5a5 r0
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test_gr_a5a5 r2
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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test_gr_a5a5 r14
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pass
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pass
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exit 0
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exit 0
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