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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# sh testcase for setdmx, setdmy, clrdmxy
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# sh testcase for setdmx, setdmy, clrdmxy
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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set_grs_a5a5
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set_grs_a5a5
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setdmx
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setdmx
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test_sr_bit_set 0x400
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test_sr_bit_set 0x400
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test_sr_bit_clear 0x800
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test_sr_bit_clear 0x800
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setdmy
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setdmy
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test_sr_bit_clear 0x400
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test_sr_bit_clear 0x400
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test_sr_bit_set 0x800
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test_sr_bit_set 0x800
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clrdmxy
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clrdmxy
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test_sr_bit_clear 0x400
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test_sr_bit_clear 0x400
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test_sr_bit_clear 0x800
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test_sr_bit_clear 0x800
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test_grs_a5a5
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test_grs_a5a5
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pass
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pass
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exit 0
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exit 0
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