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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [fcnvsd.s] - Diff between revs 24 and 33

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Rev 24	Rev 33
`# sh testcase for fcnvsd`	`# sh testcase for fcnvsd`
`# mach: sh`	`# mach: sh`
`# as(sh): -defsym sim_cpu=0`	`# as(sh): -defsym sim_cpu=0`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`
`set_grs_a5a5`	`set_grs_a5a5`
`set_fprs_a5a5`	`set_fprs_a5a5`
`double_prec`	`double_prec`
`fldi1 fr0`	`fldi1 fr0`
`flds fr0, fpul`	`flds fr0, fpul`
`fcnvsd fpul, dr2`	`fcnvsd fpul, dr2`
`assert_dpreg_i 1, dr2`	`assert_dpreg_i 1, dr2`

`# Convert back.`	`# Convert back.`
`fcnvds dr2, fpul`	`fcnvds dr2, fpul`
`fsts fpul, fr1`	`fsts fpul, fr1`
`single_prec`	`single_prec`
`assert_fpreg_i 1, fr1`	`assert_fpreg_i 1, fr1`
`fcmp/eq fr0, fr1`	`fcmp/eq fr0, fr1`
`bt .L0`	`bt .L0`
`fail`	`fail`
`.L0:`	`.L0:`
`test_grs_a5a5`	`test_grs_a5a5`
`test_fpr_a5a5 fr4`	`test_fpr_a5a5 fr4`
`test_fpr_a5a5 fr5`	`test_fpr_a5a5 fr5`
`test_fpr_a5a5 fr6`	`test_fpr_a5a5 fr6`
`test_fpr_a5a5 fr7`	`test_fpr_a5a5 fr7`
`test_fpr_a5a5 fr8`	`test_fpr_a5a5 fr8`
`test_fpr_a5a5 fr9`	`test_fpr_a5a5 fr9`
`test_fpr_a5a5 fr10`	`test_fpr_a5a5 fr10`
`test_fpr_a5a5 fr11`	`test_fpr_a5a5 fr11`
`test_fpr_a5a5 fr12`	`test_fpr_a5a5 fr12`
`test_fpr_a5a5 fr13`	`test_fpr_a5a5 fr13`
`test_fpr_a5a5 fr14`	`test_fpr_a5a5 fr14`
`test_fpr_a5a5 fr15`	`test_fpr_a5a5 fr15`
`pass`	`pass`
`exit 0`	`exit 0`

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