URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [macl.s] - Diff between revs 24 and 33

Rev 24	Rev 33
`# sh testcase for mac.l`	`# sh testcase for mac.l`
`# mach: all`	`# mach: all`
`# as(sh): -defsym sim_cpu=0`	`# as(sh): -defsym sim_cpu=0`
`# as(shdsp): -defsym sim_cpu=1 -dsp`	`# as(shdsp): -defsym sim_cpu=1 -dsp`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`
`# force S-bit clear`	`# force S-bit clear`
`clrs`	`clrs`

`init:`	`init:`
`# Prime {MACL, MACH} to #1.`	`# Prime {MACL, MACH} to #1.`
`mov #1, r0`	`mov #1, r0`
`dmulu.l r0, r0`	`dmulu.l r0, r0`

`# Set up addresses.`	`# Set up addresses.`
`mov.l pfour00, r0 ! 85`	`mov.l pfour00, r0 ! 85`
`mov.l pfour12, r1 ! 17`	`mov.l pfour12, r1 ! 17`

`test:`	`test:`
`mac.l @r0+, @r1+`	`mac.l @r0+, @r1+`

`check:`	`check:`
`# Check result.`	`# Check result.`
`assert_sreg 0, mach`	`assert_sreg 0, mach`
`assert_sreg 85*17+1, macl`	`assert_sreg 85*17+1, macl`

`# Ensure post-increment occurred.`	`# Ensure post-increment occurred.`
`assertreg0 four00+4`	`assertreg0 four00+4`
`assertreg four12+4, r1`	`assertreg four12+4, r1`

`doubleinc:`	`doubleinc:`
`mov.l pfour00, r0`	`mov.l pfour00, r0`
`mac.l @r0+, @r0+`	`mac.l @r0+, @r0+`
`assertreg0 four00+8`	`assertreg0 four00+8`


`pass`	`pass`
`exit 0`	`exit 0`

`.align 1`	`.align 1`
`four00:`	`four00:`
`.long 85`	`.long 85`
`.long 2`	`.long 2`
`four12:`	`four12:`
`.long 17`	`.long 17`
`.long 3`	`.long 3`

`.align 2`	`.align 2`
`pfour00:`	`pfour00:`
`.long four00`	`.long four00`
`pfour12:`	`pfour12:`
`.long four12`	`.long four12`