URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [movua.s] - Diff between revs 24 and 33

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 24	Rev 33
`# sh testcase for movua`	`# sh testcase for movua`
`# mach: all`	`# mach: all`
`# as(sh): -defsym sim_cpu=0`	`# as(sh): -defsym sim_cpu=0`
`# as(shdsp): -defsym sim_cpu=1 -dsp`	`# as(shdsp): -defsym sim_cpu=1 -dsp`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`
`movua_1:`	`movua_1:`
`set_grs_a5a5`	`set_grs_a5a5`
`mov.l srcp, r1`	`mov.l srcp, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x03020100`	`assertreg0 0x03020100`
`.else`	`.else`
`assertreg0 0x00010203`	`assertreg0 0x00010203`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x04030201`	`assertreg0 0x04030201`
`.else`	`.else`
`assertreg0 0x01020304`	`assertreg0 0x01020304`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x05040302`	`assertreg0 0x05040302`
`.else`	`.else`
`assertreg0 0x02030405`	`assertreg0 0x02030405`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x06050403`	`assertreg0 0x06050403`
`.else`	`.else`
`assertreg0 0x03040506`	`assertreg0 0x03040506`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x07060504`	`assertreg0 0x07060504`
`.else`	`.else`
`assertreg0 0x04050607`	`assertreg0 0x04050607`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x08070605`	`assertreg0 0x08070605`
`.else`	`.else`
`assertreg0 0x05060708`	`assertreg0 0x05060708`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x09080706`	`assertreg0 0x09080706`
`.else`	`.else`
`assertreg0 0x06070809`	`assertreg0 0x06070809`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0a090807`	`assertreg0 0x0a090807`
`.else`	`.else`
`assertreg0 0x0708090a`	`assertreg0 0x0708090a`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0b0a0908`	`assertreg0 0x0b0a0908`
`.else`	`.else`
`assertreg0 0x08090a0b`	`assertreg0 0x08090a0b`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0c0b0a09`	`assertreg0 0x0c0b0a09`
`.else`	`.else`
`assertreg0 0x090a0b0c`	`assertreg0 0x090a0b0c`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0d0c0b0a`	`assertreg0 0x0d0c0b0a`
`.else`	`.else`
`assertreg0 0x0a0b0c0d`	`assertreg0 0x0a0b0c0d`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0e0d0c0b`	`assertreg0 0x0e0d0c0b`
`.else`	`.else`
`assertreg0 0x0b0c0d0e`	`assertreg0 0x0b0c0d0e`
`.endif`	`.endif`

`add #1, r1`	`add #1, r1`
`movua.l @r1, r0`	`movua.l @r1, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x0f0e0d0c`	`assertreg0 0x0f0e0d0c`
`.else`	`.else`
`assertreg0 0x0c0d0e0f`	`assertreg0 0x0c0d0e0f`
`.endif`	`.endif`

`assertreg src+12, r1`	`assertreg src+12, r1`
`test_gr_a5a5 r2`	`test_gr_a5a5 r2`
`test_gr_a5a5 r3`	`test_gr_a5a5 r3`
`test_gr_a5a5 r4`	`test_gr_a5a5 r4`
`test_gr_a5a5 r5`	`test_gr_a5a5 r5`
`test_gr_a5a5 r6`	`test_gr_a5a5 r6`
`test_gr_a5a5 r7`	`test_gr_a5a5 r7`
`test_gr_a5a5 r8`	`test_gr_a5a5 r8`
`test_gr_a5a5 r9`	`test_gr_a5a5 r9`
`test_gr_a5a5 r10`	`test_gr_a5a5 r10`
`test_gr_a5a5 r11`	`test_gr_a5a5 r11`
`test_gr_a5a5 r12`	`test_gr_a5a5 r12`
`test_gr_a5a5 r13`	`test_gr_a5a5 r13`
`test_gr_a5a5 r14`	`test_gr_a5a5 r14`

`bra movua_4:`	`bra movua_4:`
`nop`	`nop`

`.align 0`	`.align 0`
`src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16`	`src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16`
`.align 2`	`.align 2`
`srcp: .long src`	`srcp: .long src`

`movua_4:`	`movua_4:`
`set_grs_a5a5`	`set_grs_a5a5`
`mov.l srcp2, r1`	`mov.l srcp2, r1`
`movua.l @r1+, r0`	`movua.l @r1+, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x03020100`	`assertreg0 0x03020100`
`.else`	`.else`
`assertreg0 0x00010203`	`assertreg0 0x00010203`
`.endif`	`.endif`
`assertreg src+4, r1`	`assertreg src+4, r1`

`mov.l srcp2, r1`	`mov.l srcp2, r1`
`add #1, r1`	`add #1, r1`
`movua.l @r1+, r0`	`movua.l @r1+, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x04030201`	`assertreg0 0x04030201`
`.else`	`.else`
`assertreg0 0x01020304`	`assertreg0 0x01020304`
`.endif`	`.endif`
`assertreg src+5, r1`	`assertreg src+5, r1`

`mov.l srcp2, r1`	`mov.l srcp2, r1`
`add #2, r1`	`add #2, r1`
`movua.l @r1+, r0`	`movua.l @r1+, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x05040302`	`assertreg0 0x05040302`
`.else`	`.else`
`assertreg0 0x02030405`	`assertreg0 0x02030405`
`.endif`	`.endif`
`assertreg src+6, r1`	`assertreg src+6, r1`

`mov.l srcp2, r1`	`mov.l srcp2, r1`
`add #3, r1`	`add #3, r1`
`movua.l @r1+, r0`	`movua.l @r1+, r0`
`.ifdef LITTLE`	`.ifdef LITTLE`
`assertreg0 0x06050403`	`assertreg0 0x06050403`
`.else`	`.else`
`assertreg0 0x03040506`	`assertreg0 0x03040506`
`.endif`	`.endif`
`assertreg src+7, r1`	`assertreg src+7, r1`

`test_gr_a5a5 r2`	`test_gr_a5a5 r2`
`test_gr_a5a5 r3`	`test_gr_a5a5 r3`
`test_gr_a5a5 r4`	`test_gr_a5a5 r4`
`test_gr_a5a5 r5`	`test_gr_a5a5 r5`
`test_gr_a5a5 r6`	`test_gr_a5a5 r6`
`test_gr_a5a5 r7`	`test_gr_a5a5 r7`
`test_gr_a5a5 r8`	`test_gr_a5a5 r8`
`test_gr_a5a5 r9`	`test_gr_a5a5 r9`
`test_gr_a5a5 r10`	`test_gr_a5a5 r10`
`test_gr_a5a5 r11`	`test_gr_a5a5 r11`
`test_gr_a5a5 r12`	`test_gr_a5a5 r12`
`test_gr_a5a5 r13`	`test_gr_a5a5 r13`
`test_gr_a5a5 r14`	`test_gr_a5a5 r14`

`pass`	`pass`
`exit 0`	`exit 0`

`srcp2: .long src`	`srcp2: .long src`

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [movua.s] - Diff between revs 24 and 33