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| Rev 24 |
Rev 33 |
# sh testcase for pand
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# sh testcase for pand
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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pand x0, y0, a0
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pand x0, y0, a0
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assert_sreg 0xa5a50000, a0
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assert_sreg 0xa5a50000, a0
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# 0xa5a5a5a5 & 0x5a5a5a5a == 0
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# 0xa5a5a5a5 & 0x5a5a5a5a == 0
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set_greg 0x5a5a5a5a r0
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set_greg 0x5a5a5a5a r0
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lds r0, x0
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lds r0, x0
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pand x0, y0, a0
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pand x0, y0, a0
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assert_sreg 0, a0
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assert_sreg 0, a0
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set_dcfalse
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set_dcfalse
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dct pand x0, y0, m0
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dct pand x0, y0, m0
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m0
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set_dctrue
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set_dctrue
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dct pand x0, y0, m0
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dct pand x0, y0, m0
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assert_sreg2 0, m0
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assert_sreg2 0, m0
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set_dctrue
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set_dctrue
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dcf pand x0, y0, m1
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dcf pand x0, y0, m1
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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set_dcfalse
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set_dcfalse
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dcf pand x0, y0, m1
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dcf pand x0, y0, m1
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assert_sreg2 0, m1
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assert_sreg2 0, m1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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test_grs_a5a5
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, a1
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pass
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pass
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exit 0
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exit 0
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