# sh testcase for psha <imm>
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# sh testcase for psha <imm>
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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psha_imm: ! shift arithmetic, immediate operand
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psha_imm: ! shift arithmetic, immediate operand
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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set_sreg 0x1, a0
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set_sreg 0x1, a0
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psha #0, a0
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psha #0, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #-0, a0
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psha #-0, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #1, a0
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psha #1, a0
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assert_sreg 0x2, a0
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assert_sreg 0x2, a0
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psha #-1, a0
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psha #-1, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #2, a0
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psha #2, a0
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assert_sreg 0x4, a0
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assert_sreg 0x4, a0
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psha #-2, a0
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psha #-2, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #3, a0
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psha #3, a0
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assert_sreg 0x8, a0
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assert_sreg 0x8, a0
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psha #-3, a0
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psha #-3, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #4, a0
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psha #4, a0
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assert_sreg 0x10, a0
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assert_sreg 0x10, a0
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psha #-4, a0
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psha #-4, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #5, a0
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psha #5, a0
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assert_sreg 0x20, a0
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assert_sreg 0x20, a0
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psha #-5, a0
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psha #-5, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #6, a0
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psha #6, a0
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assert_sreg 0x40, a0
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assert_sreg 0x40, a0
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psha #-6, a0
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psha #-6, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #7, a0
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psha #7, a0
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assert_sreg 0x80, a0
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assert_sreg 0x80, a0
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psha #-7, a0
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psha #-7, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #8, a0
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psha #8, a0
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assert_sreg 0x100, a0
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assert_sreg 0x100, a0
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psha #-8, a0
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psha #-8, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #9, a0
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psha #9, a0
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assert_sreg 0x200, a0
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assert_sreg 0x200, a0
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psha #-9, a0
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psha #-9, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #10, a0
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psha #10, a0
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assert_sreg 0x400, a0
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assert_sreg 0x400, a0
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psha #-10, a0
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psha #-10, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #11, a0
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psha #11, a0
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assert_sreg 0x800, a0
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assert_sreg 0x800, a0
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psha #-11, a0
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psha #-11, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #12, a0
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psha #12, a0
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assert_sreg 0x1000, a0
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assert_sreg 0x1000, a0
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psha #-12, a0
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psha #-12, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #13, a0
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psha #13, a0
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assert_sreg 0x2000, a0
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assert_sreg 0x2000, a0
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psha #-13, a0
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psha #-13, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #14, a0
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psha #14, a0
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assert_sreg 0x4000, a0
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assert_sreg 0x4000, a0
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psha #-14, a0
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psha #-14, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #15, a0
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psha #15, a0
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assert_sreg 0x8000, a0
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assert_sreg 0x8000, a0
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psha #-15, a0
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psha #-15, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #16, a0
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psha #16, a0
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assert_sreg 0x10000, a0
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assert_sreg 0x10000, a0
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psha #-16, a0
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psha #-16, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #17, a0
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psha #17, a0
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assert_sreg 0x20000, a0
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assert_sreg 0x20000, a0
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psha #-17, a0
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psha #-17, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #18, a0
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psha #18, a0
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assert_sreg 0x40000, a0
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assert_sreg 0x40000, a0
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psha #-18, a0
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psha #-18, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #19, a0
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psha #19, a0
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assert_sreg 0x80000, a0
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assert_sreg 0x80000, a0
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psha #-19, a0
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psha #-19, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #20, a0
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psha #20, a0
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assert_sreg 0x100000, a0
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assert_sreg 0x100000, a0
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psha #-20, a0
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psha #-20, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #21, a0
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psha #21, a0
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assert_sreg 0x200000, a0
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assert_sreg 0x200000, a0
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psha #-21, a0
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psha #-21, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #22, a0
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psha #22, a0
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assert_sreg 0x400000, a0
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assert_sreg 0x400000, a0
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psha #-22, a0
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psha #-22, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #23, a0
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psha #23, a0
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assert_sreg 0x800000, a0
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assert_sreg 0x800000, a0
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psha #-23, a0
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psha #-23, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #24, a0
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psha #24, a0
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assert_sreg 0x1000000, a0
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assert_sreg 0x1000000, a0
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psha #-24, a0
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psha #-24, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #25, a0
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psha #25, a0
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assert_sreg 0x2000000, a0
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assert_sreg 0x2000000, a0
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psha #-25, a0
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psha #-25, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #26, a0
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psha #26, a0
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assert_sreg 0x4000000, a0
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assert_sreg 0x4000000, a0
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psha #-26, a0
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psha #-26, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #27, a0
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psha #27, a0
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assert_sreg 0x8000000, a0
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assert_sreg 0x8000000, a0
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psha #-27, a0
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psha #-27, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #28, a0
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psha #28, a0
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assert_sreg 0x10000000, a0
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assert_sreg 0x10000000, a0
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psha #-28, a0
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psha #-28, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #29, a0
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psha #29, a0
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assert_sreg 0x20000000, a0
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assert_sreg 0x20000000, a0
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psha #-29, a0
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psha #-29, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #30, a0
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psha #30, a0
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assert_sreg 0x40000000, a0
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assert_sreg 0x40000000, a0
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psha #-30, a0
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psha #-30, a0
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assert_sreg 0x1, a0
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assert_sreg 0x1, a0
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psha #31, a0
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psha #31, a0
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assert_sreg 0x80000000, a0
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assert_sreg 0x80000000, a0
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psha #-31, a0
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psha #-31, a0
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assert_sreg 0xffffffff, a0
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assert_sreg 0xffffffff, a0
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psha #32, a0
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psha #32, a0
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assert_sreg 0x00000000, a0
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assert_sreg 0x00000000, a0
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# I don't grok what should happen here...
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# I don't grok what should happen here...
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# psha #-32, a0
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# psha #-32, a0
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# assert_sreg 0x0, a0
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# assert_sreg 0x0, a0
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test_grs_a5a5
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test_grs_a5a5
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg 0xa5a5a5a5, x0
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assert_sreg 0xa5a5a5a5, x0
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y0
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assert_sreg 0xa5a5a5a5, y0
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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pass
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pass
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exit 0
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exit 0
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