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Rev 33 |
# sh testcase for ldbank stbank resbank
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# sh testcase for ldbank stbank resbank
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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.macro SEND reg bankno regno
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.macro SEND reg bankno regno
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set_greg ((\bankno << 7) + (\regno << 2)), \reg
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set_greg ((\bankno << 7) + (\regno << 2)), \reg
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.endm
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.endm
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start
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start
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stbank_1:
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stbank_1:
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set_grs_a5a5
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set_grs_a5a5
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mov #0, r0
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mov #0, r0
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SEND r1, 0, 0
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SEND r1, 0, 0
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stbank r0, @r1
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stbank r0, @r1
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mov #1, r0
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mov #1, r0
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SEND r1, 0, 1
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SEND r1, 0, 1
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stbank r0, @r1
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stbank r0, @r1
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mov #2, r0
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mov #2, r0
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SEND r1, 0, 2
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SEND r1, 0, 2
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stbank r0, @r1
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stbank r0, @r1
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mov #3, r0
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mov #3, r0
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SEND r1, 0, 3
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SEND r1, 0, 3
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stbank r0, @r1
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stbank r0, @r1
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mov #4, r0
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mov #4, r0
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SEND r1, 0, 4
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SEND r1, 0, 4
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stbank r0, @r1
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stbank r0, @r1
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mov #5, r0
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mov #5, r0
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SEND r1, 0, 5
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SEND r1, 0, 5
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stbank r0, @r1
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stbank r0, @r1
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mov #6, r0
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mov #6, r0
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SEND r1, 0, 6
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SEND r1, 0, 6
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stbank r0, @r1
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stbank r0, @r1
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mov #7, r0
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mov #7, r0
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SEND r1, 0, 7
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SEND r1, 0, 7
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stbank r0, @r1
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stbank r0, @r1
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mov #8, r0
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mov #8, r0
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SEND r1, 0, 8
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SEND r1, 0, 8
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stbank r0, @r1
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stbank r0, @r1
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mov #9, r0
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mov #9, r0
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SEND r1, 0, 9
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SEND r1, 0, 9
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stbank r0, @r1
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stbank r0, @r1
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mov #10, r0
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mov #10, r0
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SEND r1, 0, 10
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SEND r1, 0, 10
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stbank r0, @r1
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stbank r0, @r1
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mov #11, r0
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mov #11, r0
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SEND r1, 0, 11
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SEND r1, 0, 11
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stbank r0, @r1
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stbank r0, @r1
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mov #12, r0
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mov #12, r0
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SEND r1, 0, 12
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SEND r1, 0, 12
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stbank r0, @r1
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stbank r0, @r1
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mov #13, r0
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mov #13, r0
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SEND r1, 0, 13
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SEND r1, 0, 13
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stbank r0, @r1
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stbank r0, @r1
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mov #14, r0
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mov #14, r0
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SEND r1, 0, 14
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SEND r1, 0, 14
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stbank r0, @r1
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stbank r0, @r1
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mov #15, r0
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mov #15, r0
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SEND r1, 0, 15
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SEND r1, 0, 15
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stbank r0, @r1
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stbank r0, @r1
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mov #16, r0
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mov #16, r0
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SEND r1, 0, 16
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SEND r1, 0, 16
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stbank r0, @r1
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stbank r0, @r1
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mov #17, r0
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mov #17, r0
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SEND r1, 0, 17
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SEND r1, 0, 17
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stbank r0, @r1
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stbank r0, @r1
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mov #18, r0
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mov #18, r0
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SEND r1, 0, 18
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SEND r1, 0, 18
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stbank r0, @r1
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stbank r0, @r1
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mov #19, r0
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mov #19, r0
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SEND r1, 0, 19
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SEND r1, 0, 19
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stbank r0, @r1
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stbank r0, @r1
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assertreg0 19
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assertreg0 19
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assertreg 19 << 2, r1
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assertreg 19 << 2, r1
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test_gr_a5a5 r2
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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test_gr_a5a5 r14
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ldbank_1:
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ldbank_1:
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set_grs_a5a5
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set_grs_a5a5
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SEND r1, 0, 0
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SEND r1, 0, 0
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 0
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assertreg0 0
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SEND r1, 0, 1
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SEND r1, 0, 1
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 1
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assertreg0 1
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SEND r1, 0, 2
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SEND r1, 0, 2
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 2
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assertreg0 2
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SEND r1, 0, 3
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SEND r1, 0, 3
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 3
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assertreg0 3
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SEND r1, 0, 4
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SEND r1, 0, 4
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 4
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assertreg0 4
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SEND r1, 0, 5
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SEND r1, 0, 5
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 5
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assertreg0 5
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SEND r1, 0, 6
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SEND r1, 0, 6
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 6
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assertreg0 6
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SEND r1, 0, 7
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SEND r1, 0, 7
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 7
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assertreg0 7
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SEND r1, 0, 8
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SEND r1, 0, 8
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 8
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assertreg0 8
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SEND r1, 0, 9
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SEND r1, 0, 9
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 9
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assertreg0 9
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SEND r1, 0, 10
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SEND r1, 0, 10
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 10
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assertreg0 10
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SEND r1, 0, 11
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SEND r1, 0, 11
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 11
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assertreg0 11
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SEND r1, 0, 12
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SEND r1, 0, 12
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 12
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assertreg0 12
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SEND r1, 0, 13
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SEND r1, 0, 13
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 13
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assertreg0 13
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SEND r1, 0, 14
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SEND r1, 0, 14
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 14
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assertreg0 14
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SEND r1, 0, 15
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SEND r1, 0, 15
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 15
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assertreg0 15
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SEND r1, 0, 16
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SEND r1, 0, 16
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 16
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assertreg0 16
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SEND r1, 0, 17
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SEND r1, 0, 17
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 17
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assertreg0 17
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SEND r1, 0, 18
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SEND r1, 0, 18
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 18
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assertreg0 18
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SEND r1, 0, 19
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SEND r1, 0, 19
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ldbank @r1, r0
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ldbank @r1, r0
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assertreg0 19
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assertreg0 19
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assertreg (19 << 2), r1
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assertreg (19 << 2), r1
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test_gr_a5a5 r2
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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test_gr_a5a5 r14
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resbank_1:
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resbank_1:
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set_grs_a5a5
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set_grs_a5a5
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mov #1, r0
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mov #1, r0
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trapa #13 ! magic trap, sets ibnr
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trapa #13 ! magic trap, sets ibnr
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resbank
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resbank
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assertreg0 0
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assertreg0 0
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assertreg 1, r1
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assertreg 1, r1
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assertreg 2, r2
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assertreg 2, r2
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assertreg 3, r3
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assertreg 3, r3
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assertreg 4, r4
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assertreg 4, r4
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assertreg 5, r5
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assertreg 5, r5
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assertreg 6, r6
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assertreg 6, r6
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assertreg 7, r7
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assertreg 7, r7
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assertreg 8, r8
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assertreg 8, r8
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assertreg 9, r9
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assertreg 9, r9
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assertreg 10, r10
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assertreg 10, r10
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assertreg 11, r11
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assertreg 11, r11
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assertreg 12, r12
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assertreg 12, r12
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assertreg 13, r13
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assertreg 13, r13
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assertreg 14, r14
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assertreg 14, r14
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assert_sreg 15, mach
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assert_sreg 15, mach
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assert_sreg 17, pr
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assert_sreg 17, pr
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assert_creg 18, gbr
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assert_creg 18, gbr
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assert_sreg 19, macl
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assert_sreg 19, macl
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resbank_2:
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resbank_2:
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set_grs_a5a5
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set_grs_a5a5
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movi20 #555, r0
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movi20 #555, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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add #-1, r0
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add #-1, r0
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mov.l r0, @-r15
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mov.l r0, @-r15
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set_sr_bit (1 << 14) ! set BO
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set_sr_bit (1 << 14) ! set BO
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resbank
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resbank
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assert_sreg 555, macl
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assert_sreg 555, macl
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assert_sreg 554, mach
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assert_sreg 554, mach
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assert_creg 553, gbr
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assert_creg 553, gbr
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assert_sreg 552, pr
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assert_sreg 552, pr
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assertreg 551, r14
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assertreg 551, r14
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assertreg 550, r13
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assertreg 550, r13
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assertreg 549, r12
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assertreg 549, r12
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assertreg 548, r11
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assertreg 548, r11
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assertreg 547, r10
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assertreg 547, r10
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assertreg 546, r9
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assertreg 546, r9
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assertreg 545, r8
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assertreg 545, r8
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assertreg 544, r7
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assertreg 544, r7
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assertreg 543, r6
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assertreg 543, r6
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assertreg 542, r5
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assertreg 542, r5
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assertreg 541, r4
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assertreg 541, r4
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assertreg 540, r3
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assertreg 540, r3
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assertreg 539, r2
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assertreg 539, r2
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assertreg 538, r1
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assertreg 538, r1
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assertreg0 537
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assertreg0 537
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mov r15, r0
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mov r15, r0
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assertreg0 stackt
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assertreg0 stackt
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pass
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pass
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exit 0
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exit 0
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