URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 24 |
Rev 33 |
# sh testcase for shll8
|
# sh testcase for shll8
|
# mach: all
|
# mach: all
|
# as(sh): -defsym sim_cpu=0
|
# as(sh): -defsym sim_cpu=0
|
# as(shdsp): -defsym sim_cpu=1 -dsp
|
# as(shdsp): -defsym sim_cpu=1 -dsp
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
shll8:
|
shll8:
|
set_grs_a5a5
|
set_grs_a5a5
|
mov #1, r1
|
mov #1, r1
|
shll8 r1
|
shll8 r1
|
assertreg 0x100, r1
|
assertreg 0x100, r1
|
shll8 r1
|
shll8 r1
|
assertreg 0x10000, r1
|
assertreg 0x10000, r1
|
shll8 r1
|
shll8 r1
|
assertreg 0x1000000, r1
|
assertreg 0x1000000, r1
|
shll8 r1
|
shll8 r1
|
assertreg 0, r1
|
assertreg 0, r1
|
|
|
# another:
|
# another:
|
mov #1, r1
|
mov #1, r1
|
shll8 r1
|
shll8 r1
|
mov #1, r2
|
mov #1, r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
shll r2
|
cmp/eq r1, r2
|
cmp/eq r1, r2
|
bt okay
|
bt okay
|
fail
|
fail
|
okay:
|
okay:
|
set_greg 0xa5a5a5a5, r1
|
set_greg 0xa5a5a5a5, r1
|
set_greg 0xa5a5a5a5, r2
|
set_greg 0xa5a5a5a5, r2
|
test_grs_a5a5
|
test_grs_a5a5
|
pass
|
pass
|
exit 0
|
exit 0
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.