URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh/] [shlr.s] - Diff between revs 24 and 33

Rev 24	Rev 33
`# sh testcase for shlr`	`# sh testcase for shlr`
`# mach: all`	`# mach: all`
`# as(sh): -defsym sim_cpu=0`	`# as(sh): -defsym sim_cpu=0`
`# as(shdsp): -defsym sim_cpu=1 -dsp`	`# as(shdsp): -defsym sim_cpu=1 -dsp`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`shlr:`	`shlr:`
`set_grs_a5a5`	`set_grs_a5a5`
`mov #0, r0`	`mov #0, r0`
`or #192, r0`	`or #192, r0`
`shlr r0`	`shlr r0`
`assertreg0 96`	`assertreg0 96`
`shlr r0`	`shlr r0`
`assertreg0 48`	`assertreg0 48`
`shlr r0`	`shlr r0`
`assertreg0 24`	`assertreg0 24`
`shlr r0`	`shlr r0`
`assertreg0 12`	`assertreg0 12`
`shlr r0`	`shlr r0`
`assertreg0 6`	`assertreg0 6`
`shlr r0`	`shlr r0`
`assertreg0 3`	`assertreg0 3`

`# Make sure a bit is shifted into T.`	`# Make sure a bit is shifted into T.`
`shlr r0`	`shlr r0`
`bf wrong`	`bf wrong`
`assertreg0 1`	`assertreg0 1`
`# Ditto.`	`# Ditto.`
`shlr r0`	`shlr r0`
`bf wrong`	`bf wrong`
`assertreg0 0`	`assertreg0 0`

`set_greg 0xa5a5a5a5, r0`	`set_greg 0xa5a5a5a5, r0`
`test_grs_a5a5`	`test_grs_a5a5`
`pass`	`pass`
`exit 0`	`exit 0`

`wrong:`	`wrong:`
`fail`	`fail`