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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# sh testcase for shlr2
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# sh testcase for shlr2
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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shrl2:
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shrl2:
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set_grs_a5a5
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set_grs_a5a5
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shlr2 r0
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shlr2 r0
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assertreg0 0x29696969
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assertreg0 0x29696969
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shlr2 r0
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shlr2 r0
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assertreg0 0x0a5a5a5a
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assertreg0 0x0a5a5a5a
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shlr2 r0
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shlr2 r0
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assertreg0 0x02969696
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assertreg0 0x02969696
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shlr2 r0
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shlr2 r0
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assertreg0 0x00a5a5a5
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assertreg0 0x00a5a5a5
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shlr2 r0
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shlr2 r0
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assertreg0 0x00296969
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assertreg0 0x00296969
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shlr2 r0
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shlr2 r0
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assertreg0 0x000a5a5a
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assertreg0 0x000a5a5a
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shlr2 r0
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shlr2 r0
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assertreg0 0x00029696
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assertreg0 0x00029696
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shlr2 r0
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shlr2 r0
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assertreg0 0x0000a5a5
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assertreg0 0x0000a5a5
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shlr2 r0
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shlr2 r0
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assertreg0 0x00002969
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assertreg0 0x00002969
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shlr2 r0
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shlr2 r0
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assertreg0 0x00000a5a
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assertreg0 0x00000a5a
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shlr2 r0
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shlr2 r0
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assertreg0 0x00000296
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assertreg0 0x00000296
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shlr2 r0
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shlr2 r0
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assertreg0 0x000000a5
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assertreg0 0x000000a5
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shlr2 r0
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shlr2 r0
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assertreg0 0x00000029
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assertreg0 0x00000029
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shlr2 r0
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shlr2 r0
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assertreg0 0x0000000a
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assertreg0 0x0000000a
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shlr2 r0
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shlr2 r0
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assertreg0 0x00000002
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assertreg0 0x00000002
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shlr2 r0
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shlr2 r0
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assertreg0 0
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assertreg0 0
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set_greg 0xa5a5a5a5 r0
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set_greg 0xa5a5a5a5 r0
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test_grs_a5a5
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test_grs_a5a5
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pass
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pass
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exit 0
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exit 0
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