OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [add.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# sh testcase for add $rm, $rn -*- Asm -*-
# sh testcase for add $rm, $rn -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shcompact
# as: -isa=shcompact
# ld: -m shelf32
# ld: -m shelf32
        .include "compact/testutils.inc"
        .include "compact/testutils.inc"
        start
        start
init:
init:
        # Initialise some registers with values which help us to verify
        # Initialise some registers with values which help us to verify
        # that the correct source registers are used by the ADD instruction.
        # that the correct source registers are used by the ADD instruction.
        mov #0, r0
        mov #0, r0
        mov #1, r1
        mov #1, r1
        mov #2, r2
        mov #2, r2
        mov #3, r3
        mov #3, r3
        mov #5, r5
        mov #5, r5
        mov #15, r15
        mov #15, r15
add:
add:
        # 0 + 0 = 0.
        # 0 + 0 = 0.
        add r0, r0
        add r0, r0
        assert r0, #0
        assert r0, #0
        # 0 + 1 = 1.
        # 0 + 1 = 1.
        add r0, r1
        add r0, r1
        assert r1, #1
        assert r1, #1
        # 1 + 2 = 3.
        # 1 + 2 = 3.
        add r1, r2
        add r1, r2
        assert r2, #3
        assert r2, #3
        # 3 + 5 = 8.
        # 3 + 5 = 8.
        add r3, r5
        add r3, r5
        assert r5, #8
        assert r5, #8
        # 8 + 8 = 16.
        # 8 + 8 = 16.
        add r5, r5
        add r5, r5
        assert r5, #16
        assert r5, #16
        # 15 + 1 = 16.
        # 15 + 1 = 16.
        add r15, r1
        add r15, r1
        assert r1, #16
        assert r1, #16
neg:
neg:
        mov #1, r0
        mov #1, r0
        neg r0, r0
        neg r0, r0
        mov #2, r1
        mov #2, r1
        add r0, r1
        add r0, r1
        assert r1, #1
        assert r1, #1
okay:
okay:
        pass
        pass
wrong:
wrong:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.