URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 24 |
Rev 33 |
# sh testcase for addc $rm, $rn -*- Asm -*-
|
# sh testcase for addc $rm, $rn -*- Asm -*-
|
# mach: all
|
# mach: all
|
# as: -isa=shcompact
|
# as: -isa=shcompact
|
# ld: -m shelf32
|
# ld: -m shelf32
|
|
|
.include "compact/testutils.inc"
|
.include "compact/testutils.inc"
|
|
|
# Initialise some registers with values which help us to verify
|
# Initialise some registers with values which help us to verify
|
# that the correct source registers are used by the ADDC instruction.
|
# that the correct source registers are used by the ADDC instruction.
|
|
|
.macro init
|
.macro init
|
mov #0, r0
|
mov #0, r0
|
mov #1, r1
|
mov #1, r1
|
mov #2, r2
|
mov #2, r2
|
mov #3, r3
|
mov #3, r3
|
mov #5, r5
|
mov #5, r5
|
mov #15, r15
|
mov #15, r15
|
.endm
|
.endm
|
|
|
start
|
start
|
|
|
init
|
init
|
add:
|
add:
|
clrt
|
clrt
|
addc r0, r0
|
addc r0, r0
|
assert r0, #0
|
assert r0, #0
|
clrt
|
clrt
|
addc r0, r1
|
addc r0, r1
|
assert r1, #1
|
assert r1, #1
|
clrt
|
clrt
|
addc r1, r2
|
addc r1, r2
|
assert r2, #3
|
assert r2, #3
|
clrt
|
clrt
|
addc r3, r5
|
addc r3, r5
|
assert r5, #8
|
assert r5, #8
|
clrt
|
clrt
|
addc r5, r5
|
addc r5, r5
|
assert r5, #16
|
assert r5, #16
|
clrt
|
clrt
|
addc r15, r1
|
addc r15, r1
|
assert r1, #16
|
assert r1, #16
|
|
|
init
|
init
|
addt:
|
addt:
|
sett
|
sett
|
addc r0, r0
|
addc r0, r0
|
assert r0, #1
|
assert r0, #1
|
sett
|
sett
|
addc r0, r1
|
addc r0, r1
|
assert r1, #3
|
assert r1, #3
|
sett
|
sett
|
addc r1, r2
|
addc r1, r2
|
assert r2, #6
|
assert r2, #6
|
sett
|
sett
|
addc r3, r5
|
addc r3, r5
|
assert r5, #9
|
assert r5, #9
|
sett
|
sett
|
addc r5, r5
|
addc r5, r5
|
assert r5, #19
|
assert r5, #19
|
sett
|
sett
|
addc r15, r1
|
addc r15, r1
|
assert r1, #19
|
assert r1, #19
|
|
|
bra next
|
bra next
|
nop
|
nop
|
|
|
wrong:
|
wrong:
|
fail
|
fail
|
|
|
next:
|
next:
|
init
|
init
|
large:
|
large:
|
clrt
|
clrt
|
mov #1, r0
|
mov #1, r0
|
neg r0, r0
|
neg r0, r0
|
mov #2, r1
|
mov #2, r1
|
addc r0, r1
|
addc r0, r1
|
assert r1, #1
|
assert r1, #1
|
|
|
init
|
init
|
larget:
|
larget:
|
sett
|
sett
|
mov #1, r0
|
mov #1, r0
|
neg r0, r0
|
neg r0, r0
|
mov #2, r1
|
mov #2, r1
|
addc r0, r1
|
addc r0, r1
|
assert r1, #2
|
assert r1, #2
|
|
|
okay:
|
okay:
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.