URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 33 |
# sh testcase for add #$imm8, $rn -*- Asm -*-
|
# sh testcase for add #$imm8, $rn -*- Asm -*-
|
# mach: all
|
# mach: all
|
# as: -isa=shcompact
|
# as: -isa=shcompact
|
# ld: -m shelf32
|
# ld: -m shelf32
|
|
|
.include "compact/testutils.inc"
|
.include "compact/testutils.inc"
|
|
|
start
|
start
|
init:
|
init:
|
# Initialise some registers with values which help us to verify
|
# Initialise some registers with values which help us to verify
|
# that the correct source registers are used by the ADD instruction.
|
# that the correct source registers are used by the ADD instruction.
|
mov #0, r0
|
mov #0, r0
|
mov #1, r1
|
mov #1, r1
|
mov #2, r2
|
mov #2, r2
|
mov #3, r3
|
mov #3, r3
|
mov #5, r5
|
mov #5, r5
|
mov #15, r15
|
mov #15, r15
|
|
|
addi:
|
addi:
|
# 0 + 0 = 0.
|
# 0 + 0 = 0.
|
add #0, r0
|
add #0, r0
|
assert r0, #0
|
assert r0, #0
|
|
|
# 0 + 1 = 1.
|
# 0 + 1 = 1.
|
add #0, r1
|
add #0, r1
|
assert r1, #1
|
assert r1, #1
|
|
|
# 2 + 2 = 4.
|
# 2 + 2 = 4.
|
add #2, r2
|
add #2, r2
|
assert r2, #4
|
assert r2, #4
|
|
|
# 120 + 5 = 125.
|
# 120 + 5 = 125.
|
add #120, r5
|
add #120, r5
|
assert r5, #125
|
assert r5, #125
|
|
|
large:
|
large:
|
mov #1, r0
|
mov #1, r0
|
neg r0, r0
|
neg r0, r0
|
add #2, r0
|
add #2, r0
|
assert r0, #1
|
assert r0, #1
|
|
|
okay:
|
okay:
|
pass
|
pass
|
|
|
wrong:
|
wrong:
|
fail
|
fail
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.