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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [div1.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# sh testcase for div1 $rm, $rn -*- Asm -*-
# sh testcase for div1 $rm, $rn -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shcompact
# as: -isa=shcompact
# ld: -m shelf32
# ld: -m shelf32
        .include "compact/testutils.inc"
        .include "compact/testutils.inc"
        start
        start
        mov #10, r0
        mov #10, r0
        mov #2, r1
        mov #2, r1
        div0s r0,r1
        div0s r0,r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        div1 r0, r1
        pass
        pass
 
 

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