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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [fcmpeq.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# sh testcase for fcmpeq -*- Asm -*-
# sh testcase for fcmpeq -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shcompact
# as: -isa=shcompact
# ld: -m shelf32
# ld: -m shelf32
        .include "compact/testutils.inc"
        .include "compact/testutils.inc"
        start
        start
        # 1.0 == 1.0.
        # 1.0 == 1.0.
        fldi1 fr0
        fldi1 fr0
        fldi1 fr1
        fldi1 fr1
        fcmp/eq fr0, fr1
        fcmp/eq fr0, fr1
        bf wrong
        bf wrong
        # 0.0 != 1.0.
        # 0.0 != 1.0.
        fldi0 fr0
        fldi0 fr0
        fldi1 fr1
        fldi1 fr1
        fcmp/eq fr0, fr1
        fcmp/eq fr0, fr1
        bt wrong
        bt wrong
        # 1.0 != 0.0.
        # 1.0 != 0.0.
        fldi1 fr0
        fldi1 fr0
        fldi0 fr1
        fldi0 fr1
        fcmp/eq fr0, fr1
        fcmp/eq fr0, fr1
        bt wrong
        bt wrong
        # 2.0 != 1.0
        # 2.0 != 1.0
        fldi1 fr0
        fldi1 fr0
        fadd fr0, fr0
        fadd fr0, fr0
        fldi1 fr1
        fldi1 fr1
        fcmp/eq fr0, fr1
        fcmp/eq fr0, fr1
        bt wrong
        bt wrong
        bra double
        bra double
        # delay slot
        # delay slot
        nop
        nop
wrong:
wrong:
        fail
        fail
double:
double:
        # 1.0 == 1.0
        # 1.0 == 1.0
        fldi1 fr0
        fldi1 fr0
        fldi1 fr2
        fldi1 fr2
        _s2d fr0, dr0
        _s2d fr0, dr0
        _s2d fr2, dr2
        _s2d fr2, dr2
        _setpr
        _setpr
        fcmp/eq dr0, dr2
        fcmp/eq dr0, dr2
        bf wrong
        bf wrong
        _clrpr
        _clrpr
        # 0.0 != 1.0
        # 0.0 != 1.0
        fldi0 fr0
        fldi0 fr0
        fldi1 fr2
        fldi1 fr2
        _s2d fr0, dr0
        _s2d fr0, dr0
        _s2d fr2, dr2
        _s2d fr2, dr2
        _setpr
        _setpr
        fcmp/eq dr0, dr2
        fcmp/eq dr0, dr2
        bt wrong
        bt wrong
        _clrpr
        _clrpr
        # 1.0 != 0.0
        # 1.0 != 0.0
        fldi1 fr0
        fldi1 fr0
        fldi0 fr2
        fldi0 fr2
        _s2d fr0, dr0
        _s2d fr0, dr0
        _s2d fr2, dr2
        _s2d fr2, dr2
        _setpr
        _setpr
        fcmp/eq dr0, dr2
        fcmp/eq dr0, dr2
        bt wrong2
        bt wrong2
        _clrpr
        _clrpr
        # 2.0 != 1.0
        # 2.0 != 1.0
        fldi1 fr0
        fldi1 fr0
        fadd fr0, fr0
        fadd fr0, fr0
        fldi1 fr2
        fldi1 fr2
        _s2d fr0, dr0
        _s2d fr0, dr0
        _s2d fr2, dr2
        _s2d fr2, dr2
        _setpr
        _setpr
        fcmp/eq dr0, dr2
        fcmp/eq dr0, dr2
        bt wrong2
        bt wrong2
        _clrpr
        _clrpr
okay:
okay:
        pass
        pass
wrong2:
wrong2:
        fail
        fail
 
 

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