OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [float.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# sh testcase for float -*- Asm -*-
# sh testcase for float -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shcompact
# as: -isa=shcompact
# ld: -m shelf32
# ld: -m shelf32
        .include "compact/testutils.inc"
        .include "compact/testutils.inc"
        start
        start
pos:
pos:
        mov #3, r0
        mov #3, r0
        lds r0, fpul
        lds r0, fpul
        float fpul, fr7
        float fpul, fr7
        # Check the result.
        # Check the result.
        fldi1 fr0
        fldi1 fr0
        fldi1 fr1
        fldi1 fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fcmp/eq fr1, fr7
        fcmp/eq fr1, fr7
        bf wrong
        bf wrong
neg:
neg:
        mov #3, r0
        mov #3, r0
        neg r0, r0
        neg r0, r0
        lds r0, fpul
        lds r0, fpul
        float fpul, fr7
        float fpul, fr7
        # Check the result.
        # Check the result.
        fldi1 fr0
        fldi1 fr0
        fldi1 fr1
        fldi1 fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fneg fr1
        fneg fr1
        fcmp/eq fr1, fr7
        fcmp/eq fr1, fr7
        bf wrong
        bf wrong
        bra double
        bra double
        nop
        nop
wrong:
wrong:
        fail
        fail
double:
double:
        mov #3, r0
        mov #3, r0
        lds r0, fpul
        lds r0, fpul
        _setpr
        _setpr
        float fpul, dr8
        float fpul, dr8
        _clrpr
        _clrpr
        # check the result.
        # check the result.
        fldi1 fr0
        fldi1 fr0
        fldi1 fr1
        fldi1 fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        _s2d fr1, dr2
        _s2d fr1, dr2
        fcmp/eq dr2, dr8
        fcmp/eq dr2, dr8
        bf wrong
        bf wrong
dneg:
dneg:
        mov #3, r0
        mov #3, r0
        neg r0, r0
        neg r0, r0
        lds r0, fpul
        lds r0, fpul
        _setpr
        _setpr
        float fpul, dr8
        float fpul, dr8
        _clrpr
        _clrpr
        # check the result.
        # check the result.
        fldi1 fr0
        fldi1 fr0
        fldi1 fr1
        fldi1 fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fadd fr0, fr1
        fneg fr1
        fneg fr1
        _s2d fr1, dr2
        _s2d fr1, dr2
        fcmp/eq dr2, dr8
        fcmp/eq dr2, dr8
        bf wrong
        bf wrong
okay:
okay:
        pass
        pass
wrong2:
wrong2:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.