URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 33 |
# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*-
|
# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*-
|
# mach: all
|
# mach: all
|
# as: -isa=shcompact
|
# as: -isa=shcompact
|
# ld: -m shelf32
|
# ld: -m shelf32
|
|
|
.include "compact/testutils.inc"
|
.include "compact/testutils.inc"
|
|
|
start
|
start
|
mov #30, r0
|
mov #30, r0
|
shll8 r0
|
shll8 r0
|
ldc r0, gbr
|
ldc r0, gbr
|
# Store something there first.
|
# Store something there first.
|
mov #0, r0
|
mov #0, r0
|
or #170, r0
|
or #170, r0
|
mov r0, r7
|
mov r0, r7
|
mov.b r0, @(3, gbr)
|
mov.b r0, @(3, gbr)
|
# Load it back.
|
# Load it back.
|
mov.b @(3, gbr), r0
|
mov.b @(3, gbr), r0
|
and #255, r0
|
and #255, r0
|
cmp/eq r7, r0
|
cmp/eq r7, r0
|
bf wrong
|
bf wrong
|
|
|
okay:
|
okay:
|
pass
|
pass
|
|
|
wrong:
|
wrong:
|
fail
|
fail
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.