URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 33 |
# sh testcase for subc $rm, $rn -*- Asm -*-
|
# sh testcase for subc $rm, $rn -*- Asm -*-
|
# mach: all
|
# mach: all
|
# as: -isa=shcompact
|
# as: -isa=shcompact
|
# ld: -m shelf32
|
# ld: -m shelf32
|
|
|
.include "compact/testutils.inc"
|
.include "compact/testutils.inc"
|
|
|
start
|
start
|
zero:
|
zero:
|
mov #0, r0
|
mov #0, r0
|
mov #0, r1
|
mov #0, r1
|
clrt
|
clrt
|
subc r0, r1
|
subc r0, r1
|
assert r1, #0
|
assert r1, #0
|
|
|
zerot:
|
zerot:
|
mov #0, r0
|
mov #0, r0
|
mov #0, r1
|
mov #0, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
# Invert all 1's to all 0's for ease of comparison.
|
# Invert all 1's to all 0's for ease of comparison.
|
not r1, r1
|
not r1, r1
|
assert r1, #0
|
assert r1, #0
|
|
|
null:
|
null:
|
mov #0, r0
|
mov #0, r0
|
mov #10, r1
|
mov #10, r1
|
clrt
|
clrt
|
subc r0, r1
|
subc r0, r1
|
assert r1, #10
|
assert r1, #10
|
|
|
nullt:
|
nullt:
|
mov #0, r0
|
mov #0, r0
|
mov #10, r1
|
mov #10, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
assert r1, #9
|
assert r1, #9
|
|
|
subc:
|
subc:
|
mov #10, r0
|
mov #10, r0
|
mov #0, r1
|
mov #0, r1
|
clrt
|
clrt
|
subc r0, r1
|
subc r0, r1
|
# Again, invert ..
|
# Again, invert ..
|
not r1, r1
|
not r1, r1
|
assert r1, #9
|
assert r1, #9
|
|
|
subct:
|
subct:
|
mov #10, r0
|
mov #10, r0
|
mov #0, r1
|
mov #0, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
# Again, invert ..
|
# Again, invert ..
|
not r1, r1
|
not r1, r1
|
assert r1, #10
|
assert r1, #10
|
|
|
subc2:
|
subc2:
|
mov #10, r0
|
mov #10, r0
|
mov #20, r1
|
mov #20, r1
|
clrt
|
clrt
|
subc r0, r1
|
subc r0, r1
|
assert r1, #10
|
assert r1, #10
|
|
|
subc2t:
|
subc2t:
|
mov #20, r0
|
mov #20, r0
|
mov #10, r1
|
mov #10, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
# Again, invert ..
|
# Again, invert ..
|
not r1, r1
|
not r1, r1
|
assert r1, #10
|
assert r1, #10
|
|
|
subc3:
|
subc3:
|
mov #5, r0
|
mov #5, r0
|
mov #5, r1
|
mov #5, r1
|
clrt
|
clrt
|
subc r0, r1
|
subc r0, r1
|
assert r1, #0
|
assert r1, #0
|
|
|
subc3t:
|
subc3t:
|
mov #5, r0
|
mov #5, r0
|
mov #5, r1
|
mov #5, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
# Again, invert ..
|
# Again, invert ..
|
not r1, r1
|
not r1, r1
|
assert r1, #0
|
assert r1, #0
|
|
|
large:
|
large:
|
mov #2, r0
|
mov #2, r0
|
mov #10, r1
|
mov #10, r1
|
clrt
|
clrt
|
subc r1, r0
|
subc r1, r0
|
# Again, invert ..
|
# Again, invert ..
|
not r0, r0
|
not r0, r0
|
assert r0, #7
|
assert r0, #7
|
|
|
larget:
|
larget:
|
mov #2, r0
|
mov #2, r0
|
mov #10, r1
|
mov #10, r1
|
sett
|
sett
|
subc r0, r1
|
subc r0, r1
|
assert r1, #7
|
assert r1, #7
|
|
|
okay:
|
okay:
|
pass
|
pass
|
|
|
wrong:
|
wrong:
|
fail
|
fail
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.