OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [media/] [mabsw.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# sh testcase for mabs.w $rm, $rd -*- Asm -*-
# sh testcase for mabs.w $rm, $rd -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shmedia
# as: -isa=shmedia
# ld: -m shelf64
# ld: -m shelf64
        .include "media/testutils.inc"
        .include "media/testutils.inc"
        start
        start
init:
init:
        pta wrong, tr0
        pta wrong, tr0
mabsw1:
mabsw1:
        # Pack { 1 3 5 7 } into R0.
        # Pack { 1 3 5 7 } into R0.
        _packw 1, 3, 5, 7, r0
        _packw 1, 3, 5, 7, r0
        mabs.l r0, r1
        mabs.l r0, r1
        # Test for { 1 3 5 7 } in R0.
        # Test for { 1 3 5 7 } in R0.
        _packw 1, 3, 5, 7, r2
        _packw 1, 3, 5, 7, r2
        bne r0, r2, tr0
        bne r0, r2, tr0
mabsw2:
mabsw2:
        # Pack { -1, -1, -1, -1 } into R0.
        # Pack { -1, -1, -1, -1 } into R0.
        _packw 1, 1, 1, 1, r0
        _packw 1, 1, 1, 1, r0
        # Set the left sign bit
        # Set the left sign bit
        movi 1, r1
        movi 1, r1
        shlli r1, 63, r1
        shlli r1, 63, r1
        or r0, r1, r0
        or r0, r1, r0
        mabs.w r0, r2
        mabs.w r0, r2
okay:
okay:
        pass
        pass
wrong:
wrong:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.