OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [media/] [mextr2.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*-
# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shmedia
# as: -isa=shmedia
# ld: -m shelf64
# ld: -m shelf64
        .include "media/testutils.inc"
        .include "media/testutils.inc"
        start
        start
init:
init:
        # Put a distinguised bit pattern in R0.
        # Put a distinguised bit pattern in R0.
        movi 0x1020, r0
        movi 0x1020, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x30, r0
        ori r0, 0x30, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x40, r0
        ori r0, 0x40, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x50, r0
        ori r0, 0x50, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x60, r0
        ori r0, 0x60, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x70, r0
        ori r0, 0x70, r0
        shlli r0, 8, r0
        shlli r0, 8, r0
        ori r0, 0x80, r0
        ori r0, 0x80, r0
        # Put another distinguished bit pattern in R1.
        # Put another distinguished bit pattern in R1.
        movi 0x1525, r1
        movi 0x1525, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x35, r1
        ori r1, 0x35, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x45, r1
        ori r1, 0x45, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x55, r1
        ori r1, 0x55, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x65, r1
        ori r1, 0x65, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x75, r1
        ori r1, 0x75, r1
        shlli r1, 8, r1
        shlli r1, 8, r1
        ori r1, 0x85, r1
        ori r1, 0x85, r1
mextr2:
mextr2:
        mextr2 r0, r1, r2
        mextr2 r0, r1, r2
check:
check:
        # Put the result in R3.
        # Put the result in R3.
        movi 0x3545, r3
        movi 0x3545, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x55, r3
        ori r3, 0x55, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x65, r3
        ori r3, 0x65, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x75, r3
        ori r3, 0x75, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x85, r3
        ori r3, 0x85, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x10, r3
        ori r3, 0x10, r3
        shlli r3, 8, r3
        shlli r3, 8, r3
        ori r3, 0x20, r3
        ori r3, 0x20, r3
        pta wrong, tr0
        pta wrong, tr0
        bne r2, r3, tr0
        bne r2, r3, tr0
okay:
okay:
        pass
        pass
wrong:
wrong:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.