URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 24 |
Rev 33 |
# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*-
|
# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*-
|
# mach: all
|
# mach: all
|
# as: -isa=shmedia
|
# as: -isa=shmedia
|
# ld: -m shelf64
|
# ld: -m shelf64
|
|
|
.include "media/testutils.inc"
|
.include "media/testutils.inc"
|
|
|
start
|
start
|
init:
|
init:
|
pta wrong, tr0
|
pta wrong, tr0
|
movi 27, r1
|
movi 27, r1
|
movi 0x1020, r0
|
movi 0x1020, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x30, r0
|
ori r0, 0x30, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x40, r0
|
ori r0, 0x40, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x50, r0
|
ori r0, 0x50, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x60, r0
|
ori r0, 0x60, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x70, r0
|
ori r0, 0x70, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x80, r0
|
ori r0, 0x80, r0
|
|
|
mpermw:
|
mpermw:
|
mperm.w r0, r1, r2
|
mperm.w r0, r1, r2
|
|
|
check:
|
check:
|
# Expect 0x7080506030401020.
|
# Expect 0x7080506030401020.
|
movi 0x7080, r0
|
movi 0x7080, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x50, r0
|
ori r0, 0x50, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x60, r0
|
ori r0, 0x60, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x30, r0
|
ori r0, 0x30, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x40, r0
|
ori r0, 0x40, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x10, r0
|
ori r0, 0x10, r0
|
shlli r0, 8, r0
|
shlli r0, 8, r0
|
ori r0, 0x20, r0
|
ori r0, 0x20, r0
|
|
|
bne r0, r2, tr0
|
bne r0, r2, tr0
|
|
|
okay:
|
okay:
|
pass
|
pass
|
|
|
wrong:
|
wrong:
|
fail
|
fail
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.