URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [sh64/] [misc/] [fr-dr.s] - Diff between revs 24 and 33

Rev 24	Rev 33
`# sh testcase for floating point register shared state (see below).`	`# sh testcase for floating point register shared state (see below).`
`# mach: all`	`# mach: all`
`# as: -isa=shmedia`	`# as: -isa=shmedia`
`# ld: -m shelf64`	`# ld: -m shelf64`

`# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state).`	`# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state).`
`# Hitachi SH-5 CPU volume 1, p. 15.`	`# Hitachi SH-5 CPU volume 1, p. 15.`

`.include "media/testutils.inc"`	`.include "media/testutils.inc"`

`start`	`start`

`movi 42, r0`	`movi 42, r0`
`fmov.ls r0, fr12`	`fmov.ls r0, fr12`
`# save this reg.`	`# save this reg.`
`fmov.s fr12, fr14`	`fmov.s fr12, fr14`

`movi 42, r0`	`movi 42, r0`
`fmov.qd r0, dr12`	`fmov.qd r0, dr12`

`okay:`	`okay:`
`pass`	`pass`