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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 24 |
Rev 33 |
# v850 divh
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# v850 divh
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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# Regular division - check signs
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# Regular division - check signs
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seti 6, r1
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seti 6, r1
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seti 45, r2
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seti 45, r2
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divh r1, r2
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divh r1, r2
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flags 0
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flags 0
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reg r1, 6
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reg r1, 6
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reg r2, 7
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reg r2, 7
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seti -6, r1
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seti -6, r1
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seti 45, r2
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seti 45, r2
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divh r1, r2
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divh r1, r2
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flags s
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flags s
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reg r1, -6
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reg r1, -6
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reg r2, -7
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reg r2, -7
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seti 6, r1
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seti 6, r1
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seti -45, r2
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seti -45, r2
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divh r1, r2
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divh r1, r2
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flags s
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flags s
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reg r1, 6
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reg r1, 6
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reg r2, -7
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reg r2, -7
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seti -6, r1
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seti -6, r1
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seti -45, r2
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seti -45, r2
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divh r1, r2
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divh r1, r2
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flags 0
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flags 0
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reg r1, -6
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reg r1, -6
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reg r2, 7
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reg r2, 7
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# Only the lower half of the dividend is used
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# Only the lower half of the dividend is used
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seti 0x0000fffa, r1
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seti 0x0000fffa, r1
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seti -45, r2
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seti -45, r2
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divh r1, r2
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divh r1, r2
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flags 0
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flags 0
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reg r1, 0x0000fffa
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reg r1, 0x0000fffa
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reg r2, 7
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reg r2, 7
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# If the data is divhided by zero, OV=1 and the quotient is undefined.
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# If the data is divhided by zero, OV=1 and the quotient is undefined.
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# According to NEC, the S and Z flags, and the output registers, are
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# According to NEC, the S and Z flags, and the output registers, are
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# unchanged.
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# unchanged.
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noflags
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noflags
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seti 0, r1
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seti 0, r1
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seti 45, r2
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seti 45, r2
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seti 67, r3
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seti 67, r3
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divh r1, r2
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divh r1, r2
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flags v
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flags v
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reg r2, 45
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reg r2, 45
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allflags
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allflags
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seti 0, r1
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seti 0, r1
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seti 45, r2
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seti 45, r2
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seti 67, r3
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seti 67, r3
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divh r1, r2
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divh r1, r2
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flags sat + c + v + s + z
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flags sat + c + v + s + z
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reg r2, 45
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reg r2, 45
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# Zero / (N!=0) => normal
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# Zero / (N!=0) => normal
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noflags
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noflags
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seti 45, r1
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seti 45, r1
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seti 0, r2
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seti 0, r2
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seti 67, r3
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seti 67, r3
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divh r1, r2
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divh r1, r2
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flags z
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flags z
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reg r1, 45
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reg r1, 45
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reg r2, 0
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reg r2, 0
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# Test for regular overflow
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# Test for regular overflow
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noflags
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noflags
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seti -1, r1
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seti -1, r1
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seti 0x80000000, r2
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seti 0x80000000, r2
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divh r1, r2
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divh r1, r2
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flags v + s
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flags v + s
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reg r1, -1
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reg r1, -1
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reg r2, 0x80000000
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reg r2, 0x80000000
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pass
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pass
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