;; Constraint definitions for ARM and Thumb
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;; Constraint definitions for ARM and Thumb
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;; Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
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;; Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;; Contributed by ARM Ltd.
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; The following register constraints have been used:
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;; The following register constraints have been used:
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;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
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;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
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;; - in Thumb state: h, b
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;; - in Thumb state: h, b
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;; - in both states: l, c, k
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;; - in both states: l, c, k
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;; In ARM state, 'l' is an alias for 'r'
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;; In ARM state, 'l' is an alias for 'r'
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;; The following normal constraints have been used:
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;; The following normal constraints have been used:
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;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
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;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
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;; in Thumb-1 state: I, J, K, L, M, N, O
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;; in Thumb-1 state: I, J, K, L, M, N, O
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;; The following multi-letter normal constraints have been used:
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;; The following multi-letter normal constraints have been used:
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
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;; in Thumb-1 state: Pa, Pb, Pc, Pd
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;; in Thumb-1 state: Pa, Pb, Pc, Pd
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;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
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;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
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;; The following memory constraints have been used:
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;; The following memory constraints have been used:
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;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
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;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
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;; in ARM state: Uq
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;; in ARM state: Uq
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;; in Thumb state: Uu, Uw
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;; in Thumb state: Uu, Uw
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(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
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(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
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"Legacy FPA registers @code{f0}-@code{f7}.")
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"Legacy FPA registers @code{f0}-@code{f7}.")
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(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
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(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
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"The VFP registers @code{s0}-@code{s31}.")
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"The VFP registers @code{s0}-@code{s31}.")
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(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
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(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
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"The Cirrus Maverick co-processor registers.")
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"The Cirrus Maverick co-processor registers.")
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(define_register_constraint "w"
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(define_register_constraint "w"
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"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
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"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
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"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
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"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
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(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
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(define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
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"The VFP registers @code{d0}-@code{d7}.")
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"The VFP registers @code{d0}-@code{d7}.")
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(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
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(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
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"The Intel iWMMX co-processor registers.")
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"The Intel iWMMX co-processor registers.")
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(define_register_constraint "z"
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(define_register_constraint "z"
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"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
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"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
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"The Intel iWMMX GR registers.")
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"The Intel iWMMX GR registers.")
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(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
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(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
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"In Thumb state the core registers @code{r0}-@code{r7}.")
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"In Thumb state the core registers @code{r0}-@code{r7}.")
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(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
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(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
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"In Thumb state the core registers @code{r8}-@code{r15}.")
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"In Thumb state the core registers @code{r8}-@code{r15}.")
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(define_constraint "j"
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(define_constraint "j"
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"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
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"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
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(and (match_test "TARGET_32BIT && arm_arch_thumb2")
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(and (match_test "TARGET_32BIT && arm_arch_thumb2")
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(ior (match_code "high")
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(ior (match_code "high")
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "(ival & 0xffff0000) == 0")))))
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(match_test "(ival & 0xffff0000) == 0")))))
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(define_constraint "Pj"
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(define_constraint "Pj"
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"@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
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"@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(and (match_test "TARGET_THUMB2")
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(and (match_test "TARGET_THUMB2")
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(match_test "(ival & 0xfffff000) == 0"))))
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(match_test "(ival & 0xfffff000) == 0"))))
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(define_constraint "PJ"
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(define_constraint "PJ"
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"@internal A constant that satisfies the Pj constrant if negated."
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"@internal A constant that satisfies the Pj constrant if negated."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(and (match_test "TARGET_THUMB2")
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(and (match_test "TARGET_THUMB2")
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(match_test "((-ival) & 0xfffff000) == 0"))))
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(match_test "((-ival) & 0xfffff000) == 0"))))
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(define_register_constraint "k" "STACK_REG"
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(define_register_constraint "k" "STACK_REG"
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"@internal The stack register.")
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"@internal The stack register.")
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(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
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(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
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"@internal
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"@internal
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Thumb only. The union of the low registers and the stack register.")
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Thumb only. The union of the low registers and the stack register.")
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(define_register_constraint "c" "CC_REG"
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(define_register_constraint "c" "CC_REG"
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"@internal The condition code register.")
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"@internal The condition code register.")
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(define_constraint "I"
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(define_constraint "I"
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"In ARM/Thumb-2 state a constant that can be used as an immediate value in a
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"In ARM/Thumb-2 state a constant that can be used as an immediate value in a
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Data Processing instruction. In Thumb-1 state a constant in the range
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Data Processing instruction. In Thumb-1 state a constant in the range
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0-255."
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0-255."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_32BIT ? const_ok_for_arm (ival)
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(match_test "TARGET_32BIT ? const_ok_for_arm (ival)
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: ival >= 0 && ival <= 255")))
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: ival >= 0 && ival <= 255")))
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(define_constraint "J"
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(define_constraint "J"
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"In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
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"In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
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state a constant in the range @minus{}255-@minus{}1."
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state a constant in the range @minus{}255-@minus{}1."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
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(match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
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: (ival >= -255 && ival <= -1)")))
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: (ival >= -255 && ival <= -1)")))
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(define_constraint "K"
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(define_constraint "K"
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"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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inverted. In Thumb-1 state a constant that satisfies the @code{I}
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inverted. In Thumb-1 state a constant that satisfies the @code{I}
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constraint multiplied by any power of 2."
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constraint multiplied by any power of 2."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
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(match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
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: thumb_shiftable_const (ival)")))
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: thumb_shiftable_const (ival)")))
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(define_constraint "L"
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(define_constraint "L"
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"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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"In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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negated. In Thumb-1 state a constant in the range @minus{}7-7."
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negated. In Thumb-1 state a constant in the range @minus{}7-7."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
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(match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
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: (ival >= -7 && ival <= 7)")))
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: (ival >= -7 && ival <= 7)")))
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;; The ARM state version is internal...
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;; The ARM state version is internal...
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;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
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;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
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;; power of 2.
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;; power of 2.
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(define_constraint "M"
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(define_constraint "M"
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"In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
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"In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
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(match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
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|| (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
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|| (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
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: ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
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: ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
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(define_constraint "N"
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(define_constraint "N"
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"Thumb-1 state a constant in the range 0-31."
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"Thumb-1 state a constant in the range 0-31."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
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(match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
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(define_constraint "O"
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(define_constraint "O"
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"In Thumb-1 state a constant that is a multiple of 4 in the range
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"In Thumb-1 state a constant that is a multiple of 4 in the range
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@minus{}508-508."
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@minus{}508-508."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
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(match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
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&& ((ival & 3) == 0)")))
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&& ((ival & 3) == 0)")))
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(define_constraint "Pa"
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(define_constraint "Pa"
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"@internal In Thumb-1 state a constant in the range -510 to +510"
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"@internal In Thumb-1 state a constant in the range -510 to +510"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
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(match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
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&& (ival > 255 || ival < -255)")))
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&& (ival > 255 || ival < -255)")))
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(define_constraint "Pb"
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(define_constraint "Pb"
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"@internal In Thumb-1 state a constant in the range -262 to +262"
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"@internal In Thumb-1 state a constant in the range -262 to +262"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
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(match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
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&& (ival > 255 || ival < -255)")))
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&& (ival > 255 || ival < -255)")))
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(define_constraint "Pc"
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(define_constraint "Pc"
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"@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
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"@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB1
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(match_test "TARGET_THUMB1
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&& ival > 1020 && ival <= 1275")))
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&& ival > 1020 && ival <= 1275")))
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(define_constraint "Pd"
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(define_constraint "Pd"
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"@internal In Thumb-1 state a constant in the range 0 to 7"
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"@internal In Thumb-1 state a constant in the range 0 to 7"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
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(match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
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(define_constraint "Ps"
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(define_constraint "Ps"
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"@internal In Thumb-2 state a constant in the range -255 to +255"
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"@internal In Thumb-2 state a constant in the range -255 to +255"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
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(define_constraint "Pt"
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(define_constraint "Pt"
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"@internal In Thumb-2 state a constant in the range -7 to +7"
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"@internal In Thumb-2 state a constant in the range -7 to +7"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
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(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
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(define_constraint "Pu"
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(define_constraint "Pu"
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"@internal In Thumb-2 state a constant in the range +1 to +8"
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"@internal In Thumb-2 state a constant in the range +1 to +8"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
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(match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
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(define_constraint "Pv"
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(define_constraint "Pv"
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"@internal In Thumb-2 state a constant in the range -255 to 0"
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"@internal In Thumb-2 state a constant in the range -255 to 0"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
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(define_constraint "Pw"
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(define_constraint "Pw"
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"@internal In Thumb-2 state a constant in the range -255 to -1"
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"@internal In Thumb-2 state a constant in the range -255 to -1"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
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(match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
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(define_constraint "Px"
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(define_constraint "Px"
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"@internal In Thumb-2 state a constant in the range -7 to -1"
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"@internal In Thumb-2 state a constant in the range -7 to -1"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
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(match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
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(define_constraint "Py"
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(define_constraint "Py"
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"@internal In Thumb-2 state a constant in the range 0 to 255"
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"@internal In Thumb-2 state a constant in the range 0 to 255"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
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(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
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(define_constraint "G"
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(define_constraint "G"
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"In ARM/Thumb-2 state a valid FPA immediate constant."
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"In ARM/Thumb-2 state a valid FPA immediate constant."
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
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(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
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(define_constraint "H"
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(define_constraint "H"
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"In ARM/Thumb-2 state a valid FPA immediate constant when negated."
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"In ARM/Thumb-2 state a valid FPA immediate constant when negated."
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
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(match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
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(define_constraint "Dz"
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(define_constraint "Dz"
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"@internal
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"@internal
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In ARM/Thumb-2 state a vector of constant zeros."
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In ARM/Thumb-2 state a vector of constant zeros."
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(and (match_code "const_vector")
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(and (match_code "const_vector")
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(match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
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(match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
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(define_constraint "Da"
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(define_constraint "Da"
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"@internal
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"@internal
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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be generated with two Data Processing insns."
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be generated with two Data Processing insns."
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(and (match_code "const_double,const_int,const_vector")
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(and (match_code "const_double,const_int,const_vector")
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(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
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(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
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(define_constraint "Db"
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(define_constraint "Db"
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"@internal
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"@internal
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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be generated with three Data Processing insns."
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be generated with three Data Processing insns."
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(and (match_code "const_double,const_int,const_vector")
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(and (match_code "const_double,const_int,const_vector")
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(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
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(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
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(define_constraint "Dc"
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(define_constraint "Dc"
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"@internal
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"@internal
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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be generated with four Data Processing insns. This pattern is disabled
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be generated with four Data Processing insns. This pattern is disabled
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if optimizing for space or when we have load-delay slots to fill."
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if optimizing for space or when we have load-delay slots to fill."
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(and (match_code "const_double,const_int,const_vector")
|
(and (match_code "const_double,const_int,const_vector")
|
(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
|
(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
|
&& !(optimize_size || arm_ld_sched)")))
|
&& !(optimize_size || arm_ld_sched)")))
|
|
|
(define_constraint "Di"
|
(define_constraint "Di"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_int or const_double where both the high
|
In ARM/Thumb-2 state a const_int or const_double where both the high
|
and low SImode words can be generated as immediates in 32-bit instructions."
|
and low SImode words can be generated as immediates in 32-bit instructions."
|
(and (match_code "const_double,const_int")
|
(and (match_code "const_double,const_int")
|
(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
|
(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
|
|
|
(define_constraint "Dn"
|
(define_constraint "Dn"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
|
In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
|
immediate instruction."
|
immediate instruction."
|
(and (match_code "const_vector")
|
(and (match_code "const_vector")
|
(match_test "TARGET_32BIT
|
(match_test "TARGET_32BIT
|
&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
|
&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
|
|
|
(define_constraint "Dl"
|
(define_constraint "Dl"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
|
In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
|
vbic instruction."
|
vbic instruction."
|
(and (match_code "const_vector")
|
(and (match_code "const_vector")
|
(match_test "TARGET_32BIT
|
(match_test "TARGET_32BIT
|
&& imm_for_neon_logic_operand (op, GET_MODE (op))")))
|
&& imm_for_neon_logic_operand (op, GET_MODE (op))")))
|
|
|
(define_constraint "DL"
|
(define_constraint "DL"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
|
In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
|
vand instruction."
|
vand instruction."
|
(and (match_code "const_vector")
|
(and (match_code "const_vector")
|
(match_test "TARGET_32BIT
|
(match_test "TARGET_32BIT
|
&& imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
|
&& imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
|
|
|
(define_constraint "Dv"
|
(define_constraint "Dv"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
|
In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
|
instruction."
|
instruction."
|
(and (match_code "const_double")
|
(and (match_code "const_double")
|
(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
|
(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
|
|
|
(define_constraint "Dy"
|
(define_constraint "Dy"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
|
In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
|
instruction."
|
instruction."
|
(and (match_code "const_double")
|
(and (match_code "const_double")
|
(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
|
(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
|
|
|
(define_constraint "Dt"
|
(define_constraint "Dt"
|
"@internal
|
"@internal
|
In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
|
In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
|
(and (match_code "const_double")
|
(and (match_code "const_double")
|
(match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
|
(match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
|
|
|
(define_memory_constraint "Ua"
|
(define_memory_constraint "Ua"
|
"@internal
|
"@internal
|
An address valid for loading/storing register exclusive"
|
An address valid for loading/storing register exclusive"
|
(match_operand 0 "mem_noofs_operand"))
|
(match_operand 0 "mem_noofs_operand"))
|
|
|
(define_memory_constraint "Ut"
|
(define_memory_constraint "Ut"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state an address valid for loading/storing opaque structure
|
In ARM/Thumb-2 state an address valid for loading/storing opaque structure
|
types wider than TImode."
|
types wider than TImode."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
|
(match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
|
|
|
(define_memory_constraint "Uv"
|
(define_memory_constraint "Uv"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a valid VFP load/store address."
|
In ARM/Thumb-2 state a valid VFP load/store address."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
|
(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
|
|
|
(define_memory_constraint "Uy"
|
(define_memory_constraint "Uy"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a valid iWMMX load/store address."
|
In ARM/Thumb-2 state a valid iWMMX load/store address."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
|
(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
|
|
|
(define_memory_constraint "Un"
|
(define_memory_constraint "Un"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a valid address for Neon doubleword vector
|
In ARM/Thumb-2 state a valid address for Neon doubleword vector
|
load/store instructions."
|
load/store instructions."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
|
|
|
(define_memory_constraint "Um"
|
(define_memory_constraint "Um"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a valid address for Neon element and structure
|
In ARM/Thumb-2 state a valid address for Neon element and structure
|
load/store instructions."
|
load/store instructions."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
|
|
|
(define_memory_constraint "Us"
|
(define_memory_constraint "Us"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state a valid address for non-offset loads/stores of
|
In ARM/Thumb-2 state a valid address for non-offset loads/stores of
|
quad-word values in four ARM registers."
|
quad-word values in four ARM registers."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
|
(match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
|
|
|
(define_memory_constraint "Uq"
|
(define_memory_constraint "Uq"
|
"@internal
|
"@internal
|
In ARM state an address valid in ldrsb instructions."
|
In ARM state an address valid in ldrsb instructions."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_ARM
|
(match_test "TARGET_ARM
|
&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
|
&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
|
SIGN_EXTEND, 0)")))
|
SIGN_EXTEND, 0)")))
|
|
|
(define_memory_constraint "Q"
|
(define_memory_constraint "Q"
|
"@internal
|
"@internal
|
In ARM/Thumb-2 state an address that is a single base register."
|
In ARM/Thumb-2 state an address that is a single base register."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "REG_P (XEXP (op, 0))")))
|
(match_test "REG_P (XEXP (op, 0))")))
|
|
|
(define_memory_constraint "Uu"
|
(define_memory_constraint "Uu"
|
"@internal
|
"@internal
|
In Thumb state an address that is valid in 16bit encoding."
|
In Thumb state an address that is valid in 16bit encoding."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_THUMB
|
(match_test "TARGET_THUMB
|
&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
0)")))
|
0)")))
|
|
|
; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
|
; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
|
; are actually LDM/STM instructions, so cannot be used to access unaligned
|
; are actually LDM/STM instructions, so cannot be used to access unaligned
|
; data.
|
; data.
|
(define_memory_constraint "Uw"
|
(define_memory_constraint "Uw"
|
"@internal
|
"@internal
|
In Thumb state an address that is valid in 16bit encoding, and that can be
|
In Thumb state an address that is valid in 16bit encoding, and that can be
|
used for unaligned accesses."
|
used for unaligned accesses."
|
(and (match_code "mem")
|
(and (match_code "mem")
|
(match_test "TARGET_THUMB
|
(match_test "TARGET_THUMB
|
&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
&& thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
|
0)
|
0)
|
&& GET_CODE (XEXP (op, 0)) != POST_INC")))
|
&& GET_CODE (XEXP (op, 0)) != POST_INC")))
|
|
|
;; We used to have constraint letters for S and R in ARM state, but
|
;; We used to have constraint letters for S and R in ARM state, but
|
;; all uses of these now appear to have been removed.
|
;; all uses of these now appear to have been removed.
|
|
|
;; Additionally, we used to have a Q constraint in Thumb state, but
|
;; Additionally, we used to have a Q constraint in Thumb state, but
|
;; this wasn't really a valid memory constraint. Again, all uses of
|
;; this wasn't really a valid memory constraint. Again, all uses of
|
;; this now seem to have been removed.
|
;; this now seem to have been removed.
|
|
|
