/* Fallback frame unwinding for Alpha/VMS.
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/* Fallback frame unwinding for Alpha/VMS.
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Copyright (C) 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2009
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Copyright (C) 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2009
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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<http://www.gnu.org/licenses/>. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <vms/pdscdef.h>
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#include <vms/pdscdef.h>
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#include <vms/libicb.h>
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#include <vms/libicb.h>
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#include <vms/chfctxdef.h>
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#include <vms/chfctxdef.h>
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#include <vms/chfdef.h>
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#include <vms/chfdef.h>
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#define MD_FALLBACK_FRAME_STATE_FOR alpha_vms_fallback_frame_state
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#define MD_FALLBACK_FRAME_STATE_FOR alpha_vms_fallback_frame_state
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typedef void * ADDR;
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typedef void * ADDR;
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typedef unsigned long long REG;
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typedef unsigned long long REG;
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typedef PDSCDEF * PV;
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typedef PDSCDEF * PV;
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#define REG_AT(addr) (*(REG *)(addr))
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#define REG_AT(addr) (*(REG *)(addr))
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#define ADDR_AT(addr) (*(ADDR *)(addr))
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#define ADDR_AT(addr) (*(ADDR *)(addr))
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/* Compute pointer to procedure descriptor (Procedure Value) from Frame
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/* Compute pointer to procedure descriptor (Procedure Value) from Frame
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Pointer FP, according to the rules in [ABI-3.5.1 Current Procedure]. */
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Pointer FP, according to the rules in [ABI-3.5.1 Current Procedure]. */
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#define PV_FOR(FP) \
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#define PV_FOR(FP) \
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(((FP) != 0) \
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(((FP) != 0) \
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? (((REG_AT (FP) & 0x7) == 0) ? *(PDSCDEF **)(FP) : (PDSCDEF *)(FP)) : 0)
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? (((REG_AT (FP) & 0x7) == 0) ? *(PDSCDEF **)(FP) : (PDSCDEF *)(FP)) : 0)
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extern int SYS$GL_CALL_HANDL;
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extern int SYS$GL_CALL_HANDL;
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/* This is actually defined as a "long", but in system code where longs
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/* This is actually defined as a "long", but in system code where longs
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are always 4bytes while GCC longs might be 8bytes. */
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are always 4bytes while GCC longs might be 8bytes. */
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#define UPDATE_FS_FOR_CFA_GR(FS, GRN, LOC, CFA) \
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#define UPDATE_FS_FOR_CFA_GR(FS, GRN, LOC, CFA) \
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do { \
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do { \
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(FS)->regs.reg[GRN].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[GRN].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[GRN].loc.offset = (_Unwind_Sword) ((REG) (LOC) - (REG) (CFA)); \
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(FS)->regs.reg[GRN].loc.offset = (_Unwind_Sword) ((REG) (LOC) - (REG) (CFA)); \
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} while (0);
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} while (0);
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#define GIVEUP_ON_FAILURE(STATUS) \
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#define GIVEUP_ON_FAILURE(STATUS) \
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{ if ((((STATUS) & 1) != 1)) return _URC_END_OF_STACK; }
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{ if ((((STATUS) & 1) != 1)) return _URC_END_OF_STACK; }
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#define DENOTES_EXC_DISPATCHER(PV) ((PV) == (ADDR) (REG) SYS$GL_CALL_HANDL)
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#define DENOTES_EXC_DISPATCHER(PV) ((PV) == (ADDR) (REG) SYS$GL_CALL_HANDL)
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#define RA_COLUMN (DWARF_ALT_FRAME_RETURN_COLUMN)
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#define RA_COLUMN (DWARF_ALT_FRAME_RETURN_COLUMN)
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static int
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static int
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alpha_vms_fallback_frame_state (struct _Unwind_Context *context,
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alpha_vms_fallback_frame_state (struct _Unwind_Context *context,
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_Unwind_FrameState *fs)
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_Unwind_FrameState *fs)
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{
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{
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static int eh_debug = -1;
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static int eh_debug = -1;
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/* Our goal is to update FS to reflect the state one step up CONTEXT, that
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/* Our goal is to update FS to reflect the state one step up CONTEXT, that
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is: the CFA, return address and *saved* registers locations associated
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is: the CFA, return address and *saved* registers locations associated
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with the function designated by CONTEXT->ra. We are called when the
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with the function designated by CONTEXT->ra. We are called when the
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libgcc unwinder has not found any dwarf FDE for this address, which
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libgcc unwinder has not found any dwarf FDE for this address, which
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typically happens when trying to propagate a language exception through a
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typically happens when trying to propagate a language exception through a
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signal global vector or frame based handler.
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signal global vector or frame based handler.
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The CONTEXT->reg[] entries reflect the state/location of register saves
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The CONTEXT->reg[] entries reflect the state/location of register saves
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so designate values live at the CONTEXT->ra point. Of precious value to
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so designate values live at the CONTEXT->ra point. Of precious value to
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us here is the frame pointer (r29), which gets us a procedure value. */
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us here is the frame pointer (r29), which gets us a procedure value. */
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PV pv = (context->reg[29] != 0) ? PV_FOR (ADDR_AT (context->reg[29])) : 0;
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PV pv = (context->reg[29] != 0) ? PV_FOR (ADDR_AT (context->reg[29])) : 0;
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int pkind = pv ? pv->pdsc$w_flags & 0xf : 0;
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int pkind = pv ? pv->pdsc$w_flags & 0xf : 0;
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/* VMS procedure kind, as indicated by the procedure descriptor. We only
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/* VMS procedure kind, as indicated by the procedure descriptor. We only
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know how to deal with FP_STACK or FP_REGISTER here. */
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know how to deal with FP_STACK or FP_REGISTER here. */
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ADDR new_cfa = 0;
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ADDR new_cfa = 0;
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/* CFA we will establish for the caller, computed in different ways,
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/* CFA we will establish for the caller, computed in different ways,
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e.g. depending whether we cross an exception dispatcher frame. */
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e.g. depending whether we cross an exception dispatcher frame. */
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CHFCTX *chfctx = 0;
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CHFCTX *chfctx = 0;
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/* Pointer to the VMS CHF context associated with an exception dispatcher
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/* Pointer to the VMS CHF context associated with an exception dispatcher
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frame, if we happen to come across one. */
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frame, if we happen to come across one. */
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int i,j;
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int i,j;
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if (eh_debug == -1)
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if (eh_debug == -1)
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{
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{
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char * eh_debug_env = getenv ("EH_DEBUG");
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char * eh_debug_env = getenv ("EH_DEBUG");
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eh_debug = eh_debug_env ? atoi (eh_debug_env) : 0;
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eh_debug = eh_debug_env ? atoi (eh_debug_env) : 0;
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}
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}
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if (eh_debug)
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if (eh_debug)
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printf ("MD_FALLBACK running ...\n");
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printf ("MD_FALLBACK running ...\n");
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/* We only know how to deal with stack or reg frame procedures, so give
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/* We only know how to deal with stack or reg frame procedures, so give
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up if we're handed anything else. */
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up if we're handed anything else. */
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if (pkind != PDSC$K_KIND_FP_STACK && pkind != PDSC$K_KIND_FP_REGISTER)
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if (pkind != PDSC$K_KIND_FP_STACK && pkind != PDSC$K_KIND_FP_REGISTER)
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return _URC_END_OF_STACK;
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return _URC_END_OF_STACK;
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if (eh_debug)
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if (eh_debug)
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printf ("FALLBACK: CTX FP = 0x%p, PV = 0x%p, EN = 0x%llx, RA = 0x%p\n",
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printf ("FALLBACK: CTX FP = 0x%p, PV = 0x%p, EN = 0x%llx, RA = 0x%p\n",
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ADDR_AT (context->reg[29]), pv, pv->pdsc$q_entry, context->ra);
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ADDR_AT (context->reg[29]), pv, pv->pdsc$q_entry, context->ra);
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fs->retaddr_column = RA_COLUMN;
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fs->retaddr_column = RA_COLUMN;
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/* If PV designates a VMS exception vector or condition handler, we need to
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/* If PV designates a VMS exception vector or condition handler, we need to
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do as if the caller was the signaling point and estabish the state of the
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do as if the caller was the signaling point and estabish the state of the
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intermediate VMS code (CFA, RA and saved register locations) as if it was
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intermediate VMS code (CFA, RA and saved register locations) as if it was
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a single regular function. This requires special processing.
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a single regular function. This requires special processing.
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The datastructures available from an condition dispatcher frame (signal
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The datastructures available from an condition dispatcher frame (signal
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context) do not contain the values of most callee-saved registers, so
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context) do not contain the values of most callee-saved registers, so
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whathever PV designates, we need to account for the registers it saves.
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whathever PV designates, we need to account for the registers it saves.
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Besides, we need to express all the locations with respect to a
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Besides, we need to express all the locations with respect to a
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consistent CFA value, so we compute this first. */
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consistent CFA value, so we compute this first. */
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if (DENOTES_EXC_DISPATCHER (pv))
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if (DENOTES_EXC_DISPATCHER (pv))
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{
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{
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/* The CFA to establish is the signaling point's stack pointer. We
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/* The CFA to establish is the signaling point's stack pointer. We
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compute it using the system invocation context unwinding services and
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compute it using the system invocation context unwinding services and
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save the CHF context data pointer along the way for later uses. */
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save the CHF context data pointer along the way for later uses. */
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INVO_CONTEXT_BLK icb;
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INVO_CONTEXT_BLK icb;
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int status, invo_handle;
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int status, invo_handle;
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if (eh_debug)
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if (eh_debug)
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printf ("FALLBACK: SYS$HANDLER\n");
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printf ("FALLBACK: SYS$HANDLER\n");
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icb.libicb$q_ireg [29] = REG_AT (context->reg[29]);
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icb.libicb$q_ireg [29] = REG_AT (context->reg[29]);
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icb.libicb$q_ireg [30] = 0;
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icb.libicb$q_ireg [30] = 0;
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invo_handle = LIB$GET_INVO_HANDLE (&icb);
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invo_handle = LIB$GET_INVO_HANDLE (&icb);
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status = LIB$GET_INVO_CONTEXT (invo_handle, &icb);
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status = LIB$GET_INVO_CONTEXT (invo_handle, &icb);
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GIVEUP_ON_FAILURE (status);
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GIVEUP_ON_FAILURE (status);
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chfctx = (CHFCTX *) icb.libicb$ph_chfctx_addr;
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chfctx = (CHFCTX *) icb.libicb$ph_chfctx_addr;
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status = LIB$GET_PREV_INVO_CONTEXT (&icb);
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status = LIB$GET_PREV_INVO_CONTEXT (&icb);
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GIVEUP_ON_FAILURE (status);
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GIVEUP_ON_FAILURE (status);
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new_cfa = (ADDR) icb.libicb$q_ireg[30];
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new_cfa = (ADDR) icb.libicb$q_ireg[30];
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}
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}
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else
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else
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{
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{
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/* The CFA to establish is the SP value on entry of the procedure
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/* The CFA to establish is the SP value on entry of the procedure
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designated by PV, which we compute as the corresponding frame base
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designated by PV, which we compute as the corresponding frame base
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register value + frame size. Note that the frame base may differ
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register value + frame size. Note that the frame base may differ
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from CONTEXT->cfa, typically if the caller has performed dynamic
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from CONTEXT->cfa, typically if the caller has performed dynamic
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stack allocations. */
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stack allocations. */
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int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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new_cfa = base_addr + pv->pdsc$l_size;
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new_cfa = base_addr + pv->pdsc$l_size;
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}
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}
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/* State to compute the caller's CFA by adding an offset to the current
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/* State to compute the caller's CFA by adding an offset to the current
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one in CONTEXT. */
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one in CONTEXT. */
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_reg = __builtin_dwarf_sp_column ();
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fs->regs.cfa_reg = __builtin_dwarf_sp_column ();
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fs->regs.cfa_offset = new_cfa - context->cfa;
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fs->regs.cfa_offset = new_cfa - context->cfa;
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/* Regular unwind first, accounting for the register saves performed by
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/* Regular unwind first, accounting for the register saves performed by
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the procedure designated by PV. */
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the procedure designated by PV. */
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switch (pkind)
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switch (pkind)
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{
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{
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case PDSC$K_KIND_FP_STACK:
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case PDSC$K_KIND_FP_STACK:
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{
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{
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/* The saved registers are all located in the Register Save Area,
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/* The saved registers are all located in the Register Save Area,
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except for the procedure value register (R27) found at the frame
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except for the procedure value register (R27) found at the frame
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base address. */
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base address. */
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int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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ADDR rsa_addr = base_addr + pv->pdsc$w_rsa_offset;
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ADDR rsa_addr = base_addr + pv->pdsc$w_rsa_offset;
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if (eh_debug)
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if (eh_debug)
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printf ("FALLBACK: STACK frame procedure\n");
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printf ("FALLBACK: STACK frame procedure\n");
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UPDATE_FS_FOR_CFA_GR (fs, 27, base_addr, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 27, base_addr, new_cfa);
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/* The first RSA entry is for the return address register, R26. */
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/* The first RSA entry is for the return address register, R26. */
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UPDATE_FS_FOR_CFA_GR (fs, 26, rsa_addr, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 26, rsa_addr, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, rsa_addr, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, rsa_addr, new_cfa);
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/* The following entries are for registers marked as saved according
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/* The following entries are for registers marked as saved according
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to ireg_mask. */
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to ireg_mask. */
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for (i = 0, j = 0; i < 32; i++)
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for (i = 0, j = 0; i < 32; i++)
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if ((1 << i) & pv->pdsc$l_ireg_mask)
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if ((1 << i) & pv->pdsc$l_ireg_mask)
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UPDATE_FS_FOR_CFA_GR (fs, i, rsa_addr + 8 * ++j, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, i, rsa_addr + 8 * ++j, new_cfa);
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/* ??? floating point registers ? */
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/* ??? floating point registers ? */
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break;
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break;
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}
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}
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case PDSC$K_KIND_FP_REGISTER:
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case PDSC$K_KIND_FP_REGISTER:
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{
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{
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if (eh_debug)
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if (eh_debug)
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printf ("FALLBACK: REGISTER frame procedure\n");
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printf ("FALLBACK: REGISTER frame procedure\n");
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fs->regs.reg[RA_COLUMN].how = REG_SAVED_REG;
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fs->regs.reg[RA_COLUMN].how = REG_SAVED_REG;
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fs->regs.reg[RA_COLUMN].loc.reg = pv->pdsc$b_save_ra;
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fs->regs.reg[RA_COLUMN].loc.reg = pv->pdsc$b_save_ra;
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fs->regs.reg[29].how = REG_SAVED_REG;
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fs->regs.reg[29].how = REG_SAVED_REG;
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fs->regs.reg[29].loc.reg = pv->pdsc$b_save_fp;
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fs->regs.reg[29].loc.reg = pv->pdsc$b_save_fp;
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break;
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break;
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}
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}
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default:
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default:
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/* Should never reach here. */
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/* Should never reach here. */
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return _URC_END_OF_STACK;
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return _URC_END_OF_STACK;
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}
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}
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/* If PV designates an exception dispatcher, we have to adjust the return
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/* If PV designates an exception dispatcher, we have to adjust the return
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address column to get at the signal occurrence point, and account for
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address column to get at the signal occurrence point, and account for
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for what the CHF context contains. */
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for what the CHF context contains. */
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if (DENOTES_EXC_DISPATCHER (pv))
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if (DENOTES_EXC_DISPATCHER (pv))
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{
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{
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/* The PC of the instruction causing the condition is available from the
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/* The PC of the instruction causing the condition is available from the
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signal argument vector. Extra saved register values are available
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signal argument vector. Extra saved register values are available
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from the mechargs array. */
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from the mechargs array. */
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CHF$SIGNAL_ARRAY *sigargs
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CHF$SIGNAL_ARRAY *sigargs
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= (CHF$SIGNAL_ARRAY *) chfctx->chfctx$q_sigarglst;
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= (CHF$SIGNAL_ARRAY *) chfctx->chfctx$q_sigarglst;
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CHF$MECH_ARRAY *mechargs
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CHF$MECH_ARRAY *mechargs
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= (CHF$MECH_ARRAY *) chfctx->chfctx$q_mcharglst;
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= (CHF$MECH_ARRAY *) chfctx->chfctx$q_mcharglst;
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ADDR condpc_addr
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ADDR condpc_addr
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= &((int *)(&sigargs->chf$l_sig_name)) [sigargs->chf$is_sig_args-2];
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= &((int *)(&sigargs->chf$l_sig_name)) [sigargs->chf$is_sig_args-2];
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ADDR rei_frame_addr = (void *) mechargs->chf$q_mch_esf_addr;
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ADDR rei_frame_addr = (void *) mechargs->chf$q_mch_esf_addr;
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/* Adjust the return address location. */
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/* Adjust the return address location. */
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UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, condpc_addr, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, condpc_addr, new_cfa);
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|
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/* The frame pointer at the condition point is available from the
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/* The frame pointer at the condition point is available from the
|
chf context directly. */
|
chf context directly. */
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|
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UPDATE_FS_FOR_CFA_GR (fs, 29, &chfctx->chfctx$q_expt_fp, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 29, &chfctx->chfctx$q_expt_fp, new_cfa);
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|
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/* Registers available from the mechargs array. */
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/* Registers available from the mechargs array. */
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UPDATE_FS_FOR_CFA_GR (fs, 0, &mechargs->chf$q_mch_savr0, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 0, &mechargs->chf$q_mch_savr0, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 1, &mechargs->chf$q_mch_savr1, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 1, &mechargs->chf$q_mch_savr1, new_cfa);
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|
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UPDATE_FS_FOR_CFA_GR (fs, 16, &mechargs->chf$q_mch_savr16, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 16, &mechargs->chf$q_mch_savr16, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 17, &mechargs->chf$q_mch_savr17, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 17, &mechargs->chf$q_mch_savr17, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 18, &mechargs->chf$q_mch_savr18, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 18, &mechargs->chf$q_mch_savr18, new_cfa);
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UPDATE_FS_FOR_CFA_GR (fs, 19, &mechargs->chf$q_mch_savr19, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 19, &mechargs->chf$q_mch_savr19, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 20, &mechargs->chf$q_mch_savr20, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 20, &mechargs->chf$q_mch_savr20, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 21, &mechargs->chf$q_mch_savr21, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 21, &mechargs->chf$q_mch_savr21, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 22, &mechargs->chf$q_mch_savr22, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 22, &mechargs->chf$q_mch_savr22, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 23, &mechargs->chf$q_mch_savr23, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 23, &mechargs->chf$q_mch_savr23, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 24, &mechargs->chf$q_mch_savr24, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 24, &mechargs->chf$q_mch_savr24, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 25, &mechargs->chf$q_mch_savr25, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 25, &mechargs->chf$q_mch_savr25, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 26, &mechargs->chf$q_mch_savr26, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 26, &mechargs->chf$q_mch_savr26, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 27, &mechargs->chf$q_mch_savr27, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 27, &mechargs->chf$q_mch_savr27, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 28, &mechargs->chf$q_mch_savr28, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, 28, &mechargs->chf$q_mch_savr28, new_cfa);
|
|
|
/* Registers R2 to R7 are available from the rei frame pointer. */
|
/* Registers R2 to R7 are available from the rei frame pointer. */
|
|
|
for (i = 2; i <= 7; i ++)
|
for (i = 2; i <= 7; i ++)
|
UPDATE_FS_FOR_CFA_GR (fs, i, rei_frame_addr+(i - 2)*8, new_cfa);
|
UPDATE_FS_FOR_CFA_GR (fs, i, rei_frame_addr+(i - 2)*8, new_cfa);
|
|
|
/* ??? floating point registers ? */
|
/* ??? floating point registers ? */
|
}
|
}
|
|
|
return _URC_NO_REASON;
|
return _URC_NO_REASON;
|
}
|
}
|
|
|
|
|
|
|
|
|
