OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [config/] [arc/] [lib1funcs.asm] - Diff between revs 282 and 338

Only display areas with differences | Details | Blame | View Log

Rev 282 Rev 338
; libgcc routines for ARC cpu.
; libgcc routines for ARC cpu.
/* Copyright (C) 1995, 1997,2004, 2009 Free Software Foundation, Inc.
/* Copyright (C) 1995, 1997,2004, 2009 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
Free Software Foundation; either version 3, or (at your option) any
later version.
later version.
This file is distributed in the hope that it will be useful, but
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for more details.
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
.  */
#ifdef  L_mulsi3
#ifdef  L_mulsi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___mulsi3
        .global ___mulsi3
___mulsi3:
___mulsi3:
/* This the simple version.
/* This the simple version.
  while (a)
  while (a)
    {
    {
      if (a & 1)
      if (a & 1)
        r += b;
        r += b;
      a >>= 1;
      a >>= 1;
      b <<= 1;
      b <<= 1;
    }
    }
*/
*/
        mov r2,0                ; Accumulate result here.
        mov r2,0                ; Accumulate result here.
.Lloop:
.Lloop:
        sub.f 0,r0,0            ; while (a)
        sub.f 0,r0,0            ; while (a)
        nop
        nop
        beq.nd .Ldone
        beq.nd .Ldone
        and.f 0,r0,1            ; if (a & 1)
        and.f 0,r0,1            ; if (a & 1)
        add.nz r2,r2,r1         ; r += b
        add.nz r2,r2,r1         ; r += b
        lsr r0,r0               ; a >>= 1
        lsr r0,r0               ; a >>= 1
        b.d .Lloop
        b.d .Lloop
        lsl r1,r1               ; b <<= 1
        lsl r1,r1               ; b <<= 1
.Ldone:
.Ldone:
        j.d blink
        j.d blink
        mov r0,r2
        mov r0,r2
#endif
#endif
#endif /* L_mulsi3 */
#endif /* L_mulsi3 */
#ifdef  L_umulsidi3
#ifdef  L_umulsidi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___umulsidi3
        .global ___umulsidi3
___umulsidi3:
___umulsidi3:
/* This the simple version.
/* This the simple version.
  while (a)
  while (a)
    {
    {
      if (a & 1)
      if (a & 1)
        r += b;
        r += b;
      a >>= 1;
      a >>= 1;
      b <<= 1;
      b <<= 1;
    }
    }
*/
*/
        mov r2,0                ; Top part of b.
        mov r2,0                ; Top part of b.
        mov r3,0                ; Accumulate result here.
        mov r3,0                ; Accumulate result here.
        mov r4,0
        mov r4,0
.Lloop:
.Lloop:
        sub.f 0,r0,0            ; while (a)
        sub.f 0,r0,0            ; while (a)
        nop
        nop
        beq.nd .Ldone
        beq.nd .Ldone
        and.f 0,r0,1            ; if (a & 1)
        and.f 0,r0,1            ; if (a & 1)
        sub.f 0,r0,0
        sub.f 0,r0,0
        nop
        nop
        beq .Ldontadd
        beq .Ldontadd
        add.f r4,r4,r1          ; r += b
        add.f r4,r4,r1          ; r += b
        adc   r3,r3,r2
        adc   r3,r3,r2
.Ldontadd:
.Ldontadd:
        lsr r0,r0               ; a >>= 1
        lsr r0,r0               ; a >>= 1
        lsl.f r1,r1             ; b <<= 1
        lsl.f r1,r1             ; b <<= 1
        b.d .Lloop
        b.d .Lloop
        rlc r2,r2
        rlc r2,r2
.Ldone:
.Ldone:
#ifdef __big_endian__
#ifdef __big_endian__
        mov r1,r4
        mov r1,r4
        j.d blink
        j.d blink
        mov r0,r3
        mov r0,r3
#else
#else
        mov r0,r4
        mov r0,r4
        j.d blink
        j.d blink
        mov r1,r3
        mov r1,r3
#endif
#endif
#endif
#endif
#endif /* L_umulsidi3 */
#endif /* L_umulsidi3 */
#ifdef L_divmod_tools
#ifdef L_divmod_tools
; Utilities used by all routines.
; Utilities used by all routines.
        .section .text
        .section .text
        .align 4
        .align 4
; inputs: r0 = numerator, r1 = denominator
; inputs: r0 = numerator, r1 = denominator
; outputs: positive r0/r1,
; outputs: positive r0/r1,
;          r6.bit1 = sign of numerator, r6.bit0 = sign of result
;          r6.bit1 = sign of numerator, r6.bit0 = sign of result
        .global ___divnorm
        .global ___divnorm
___divnorm:
___divnorm:
        mov r6,0                ; keep sign in r6
        mov r6,0                ; keep sign in r6
        sub.f 0,r0,0            ; is numerator -ve?
        sub.f 0,r0,0            ; is numerator -ve?
        sub.lt r0,0,r0          ; negate numerator
        sub.lt r0,0,r0          ; negate numerator
        mov.lt r6,3             ; sign is -ve
        mov.lt r6,3             ; sign is -ve
        sub.f 0,r1,0            ; is denominator -ve?
        sub.f 0,r1,0            ; is denominator -ve?
        sub.lt r1,0,r1          ; negate denominator
        sub.lt r1,0,r1          ; negate denominator
        xor.lt r6,r6,1          ; toggle sign
        xor.lt r6,r6,1          ; toggle sign
        j.nd blink
        j.nd blink
/*
/*
unsigned long
unsigned long
udivmodsi4(int modwanted, unsigned long num, unsigned long den)
udivmodsi4(int modwanted, unsigned long num, unsigned long den)
{
{
  unsigned long bit = 1;
  unsigned long bit = 1;
  unsigned long res = 0;
  unsigned long res = 0;
  while (den < num && bit && !(den & (1L<<31)))
  while (den < num && bit && !(den & (1L<<31)))
    {
    {
      den <<=1;
      den <<=1;
      bit <<=1;
      bit <<=1;
    }
    }
  while (bit)
  while (bit)
    {
    {
      if (num >= den)
      if (num >= den)
        {
        {
          num -= den;
          num -= den;
          res |= bit;
          res |= bit;
        }
        }
      bit >>=1;
      bit >>=1;
      den >>=1;
      den >>=1;
    }
    }
  if (modwanted) return num;
  if (modwanted) return num;
  return res;
  return res;
}
}
*/
*/
; inputs: r0 = numerator, r1 = denominator
; inputs: r0 = numerator, r1 = denominator
; outputs: r0 = quotient, r1 = remainder, r2/r3 trashed
; outputs: r0 = quotient, r1 = remainder, r2/r3 trashed
        .global ___udivmodsi4
        .global ___udivmodsi4
___udivmodsi4:
___udivmodsi4:
        mov r2,1                ; bit = 1
        mov r2,1                ; bit = 1
        mov r3,0                ; res = 0
        mov r3,0                ; res = 0
.Lloop1:
.Lloop1:
        sub.f 0,r1,r0           ; while (den < num
        sub.f 0,r1,r0           ; while (den < num
        nop
        nop
        bnc.nd .Lloop2
        bnc.nd .Lloop2
        sub.f 0,r2,0            ; && bit
        sub.f 0,r2,0            ; && bit
        nop
        nop
        bz.nd .Lloop2
        bz.nd .Lloop2
        lsl.f 0,r1              ; && !(den & (1<<31))
        lsl.f 0,r1              ; && !(den & (1<<31))
        nop
        nop
        bc.nd .Lloop2
        bc.nd .Lloop2
        lsl r1,r1               ; den <<= 1
        lsl r1,r1               ; den <<= 1
        b.d .Lloop1
        b.d .Lloop1
        lsl r2,r2               ; bit <<= 1
        lsl r2,r2               ; bit <<= 1
.Lloop2:
.Lloop2:
        sub.f 0,r2,0            ; while (bit)
        sub.f 0,r2,0            ; while (bit)
        nop
        nop
        bz.nd .Ldivmodend
        bz.nd .Ldivmodend
        sub.f 0,r0,r1           ; if (num >= den)
        sub.f 0,r0,r1           ; if (num >= den)
        nop
        nop
        bc.nd .Lshiftdown
        bc.nd .Lshiftdown
        sub r0,r0,r1            ; num -= den
        sub r0,r0,r1            ; num -= den
        or r3,r3,r2             ; res |= bit
        or r3,r3,r2             ; res |= bit
.Lshiftdown:
.Lshiftdown:
        lsr r2,r2               ; bit >>= 1
        lsr r2,r2               ; bit >>= 1
        b.d .Lloop2
        b.d .Lloop2
        lsr r1,r1               ; den >>= 1
        lsr r1,r1               ; den >>= 1
.Ldivmodend:
.Ldivmodend:
        mov r1,r0               ; r1 = mod
        mov r1,r0               ; r1 = mod
        j.d blink
        j.d blink
        mov r0,r3               ; r0 = res
        mov r0,r3               ; r0 = res
#endif
#endif
#ifdef  L_udivsi3
#ifdef  L_udivsi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___udivsi3
        .global ___udivsi3
___udivsi3:
___udivsi3:
        mov r7,blink
        mov r7,blink
        bl.nd ___udivmodsi4
        bl.nd ___udivmodsi4
        j.nd r7
        j.nd r7
#endif
#endif
#endif /* L_udivsi3 */
#endif /* L_udivsi3 */
#ifdef  L_divsi3
#ifdef  L_divsi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___divsi3
        .global ___divsi3
___divsi3:
___divsi3:
        mov r7,blink
        mov r7,blink
        bl.nd ___divnorm
        bl.nd ___divnorm
        bl.nd ___udivmodsi4
        bl.nd ___udivmodsi4
        and.f 0,r6,1
        and.f 0,r6,1
        sub.nz r0,0,r0          ; cannot go in delay slot, has limm value
        sub.nz r0,0,r0          ; cannot go in delay slot, has limm value
        j.nd r7
        j.nd r7
#endif
#endif
#endif /* L_divsi3 */
#endif /* L_divsi3 */
#ifdef  L_umodsi3
#ifdef  L_umodsi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___umodsi3
        .global ___umodsi3
___umodsi3:
___umodsi3:
        mov r7,blink
        mov r7,blink
        bl.nd ___udivmodsi4
        bl.nd ___udivmodsi4
        j.d r7
        j.d r7
        mov r0,r1
        mov r0,r1
#endif
#endif
#endif /* L_umodsi3 */
#endif /* L_umodsi3 */
#ifdef  L_modsi3
#ifdef  L_modsi3
        .section .text
        .section .text
        .align 4
        .align 4
#ifdef __base__
#ifdef __base__
        .cpu base
        .cpu base
        .global ___modsi3
        .global ___modsi3
___modsi3:
___modsi3:
        mov r7,blink
        mov r7,blink
        bl.nd ___divnorm
        bl.nd ___divnorm
        bl.nd ___udivmodsi4
        bl.nd ___udivmodsi4
        and.f 0,r6,2
        and.f 0,r6,2
        sub.nz r1,0,r1
        sub.nz r1,0,r1
        j.d r7
        j.d r7
        mov r0,r1
        mov r0,r1
#endif
#endif
#endif /* L_modsi3 */
#endif /* L_modsi3 */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.