/* Definitions of target machine GNU compiler. IA-64 version.
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/* Definitions of target machine GNU compiler. IA-64 version.
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Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by James E. Wilson and
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Contributed by James E. Wilson and
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David Mosberger .
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David Mosberger .
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GCC is distributed in the hope that it will be useful,
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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along with GCC; see the file COPYING3. If not see
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. */
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. */
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/* IA64 requires both XF and TF modes.
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/* IA64 requires both XF and TF modes.
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XFmode is __float80 is IEEE extended; TFmode is __float128
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XFmode is __float80 is IEEE extended; TFmode is __float128
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is IEEE quad. Both these modes occupy 16 bytes, but XFmode
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is IEEE quad. Both these modes occupy 16 bytes, but XFmode
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only has 80 significant bits. RFmode is __fpreg is IA64 internal
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only has 80 significant bits. RFmode is __fpreg is IA64 internal
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register format with 82 significant bits but otherwise handled like
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register format with 82 significant bits but otherwise handled like
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XFmode. */
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XFmode. */
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FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format);
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FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format);
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FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format);
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FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format);
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FLOAT_MODE (TF, 16, ieee_quad_format);
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FLOAT_MODE (TF, 16, ieee_quad_format);
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/* The above produces:
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/* The above produces:
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mode ILP32 size/align LP64 size/align
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mode ILP32 size/align LP64 size/align
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XF 16/16 16/16
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XF 16/16 16/16
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TF 16/16 16/16
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TF 16/16 16/16
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psABI expectations:
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psABI expectations:
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mode ILP32 size/align LP64 size/align
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mode ILP32 size/align LP64 size/align
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XF 12/4 -
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XF 12/4 -
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TF - -
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TF - -
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HPUX expectations:
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HPUX expectations:
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mode ILP32 size/align LP64 size/align
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mode ILP32 size/align LP64 size/align
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XF - -
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XF - -
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TF 16/8 -
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TF 16/8 -
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We fix this up here. */
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We fix this up here. */
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ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX)
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ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX)
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? &ieee_extended_intel_96_format
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? &ieee_extended_intel_96_format
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: &ieee_extended_intel_128_format);
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: &ieee_extended_intel_128_format);
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ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX)
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ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX)
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? &ieee_extended_intel_96_format
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? &ieee_extended_intel_96_format
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: &ieee_extended_intel_128_format);
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: &ieee_extended_intel_128_format);
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ADJUST_BYTESIZE (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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ADJUST_BYTESIZE (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
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ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
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ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16);
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ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16);
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/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
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/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
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INT_MODE (OI, 32);
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INT_MODE (OI, 32);
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/* Add any extra modes needed to represent the condition code.
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/* Add any extra modes needed to represent the condition code.
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CCImode is used to mark a single predicate register instead
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CCImode is used to mark a single predicate register instead
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of a register pair. This is currently only used in reg_raw_mode
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of a register pair. This is currently only used in reg_raw_mode
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so that flow doesn't do something stupid. */
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so that flow doesn't do something stupid. */
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CC_MODE (CCI);
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CC_MODE (CCI);
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/* Vector modes. */
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/* Vector modes. */
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VECTOR_MODES (INT, 4); /* V4QI V2HI */
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VECTOR_MODES (INT, 4); /* V4QI V2HI */
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VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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VECTOR_MODE (INT, QI, 16);
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VECTOR_MODE (INT, QI, 16);
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VECTOR_MODE (INT, HI, 8);
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VECTOR_MODE (INT, HI, 8);
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VECTOR_MODE (INT, SI, 4);
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VECTOR_MODE (INT, SI, 4);
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VECTOR_MODE (FLOAT, SF, 2);
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VECTOR_MODE (FLOAT, SF, 2);
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VECTOR_MODE (FLOAT, SF, 4);
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VECTOR_MODE (FLOAT, SF, 4);
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