#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE unsigned long
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#define _FP_W_TYPE unsigned long
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#define _FP_WS_TYPE signed long
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#define _FP_WS_TYPE signed long
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#define _FP_I_TYPE long
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#define _FP_I_TYPE long
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typedef int TItype __attribute__ ((mode (TI)));
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typedef int TItype __attribute__ ((mode (TI)));
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typedef unsigned int UTItype __attribute__ ((mode (TI)));
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typedef unsigned int UTItype __attribute__ ((mode (TI)));
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#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
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#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
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/* The type of the result of a floating point comparison. This must
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/* The type of the result of a floating point comparison. This must
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match `__libgcc_cmp_return__' in GCC for the target. */
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match `__libgcc_cmp_return__' in GCC for the target. */
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typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
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typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
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#define CMPtype __gcc_CMPtype
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#define CMPtype __gcc_CMPtype
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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#define _FP_NANFRAC_S _FP_QNANBIT_S
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#define _FP_NANFRAC_S _FP_QNANBIT_S
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#define _FP_NANFRAC_D _FP_QNANBIT_D
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#define _FP_NANFRAC_D _FP_QNANBIT_D
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#define _FP_NANFRAC_E _FP_QNANBIT_E, 0
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#define _FP_NANFRAC_E _FP_QNANBIT_E, 0
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#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
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#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_D 1
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#define _FP_NANSIGN_D 1
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#define _FP_NANSIGN_E 1
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#define _FP_NANSIGN_E 1
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#define _FP_NANSIGN_Q 1
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#define _FP_NANSIGN_Q 1
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#define _FP_KEEPNANFRACP 1
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#define _FP_KEEPNANFRACP 1
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/* Here is something Intel misdesigned: the specs don't define
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/* Here is something Intel misdesigned: the specs don't define
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the case where we have two NaNs with same mantissas, but
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the case where we have two NaNs with same mantissas, but
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different sign. Different operations pick up different NaNs. */
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different sign. Different operations pick up different NaNs. */
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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do { \
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if (_FP_FRAC_GT_##wc(X, Y) \
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if (_FP_FRAC_GT_##wc(X, Y) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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{ \
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{ \
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R##_s = X##_s; \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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} \
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else \
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else \
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{ \
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{ \
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R##_s = Y##_s; \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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} \
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R##_c = FP_CLS_NAN; \
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R##_c = FP_CLS_NAN; \
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} while (0)
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} while (0)
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#define FP_EX_INVALID 0x01
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#define FP_EX_INVALID 0x01
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#define FP_EX_DENORM 0x02
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#define FP_EX_DENORM 0x02
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#define FP_EX_DIVZERO 0x04
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#define FP_EX_DIVZERO 0x04
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#define FP_EX_OVERFLOW 0x08
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#define FP_EX_OVERFLOW 0x08
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#define FP_EX_UNDERFLOW 0x10
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#define FP_EX_UNDERFLOW 0x10
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#define FP_EX_INEXACT 0x20
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#define FP_EX_INEXACT 0x20
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#define FP_HANDLE_EXCEPTIONS \
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#define FP_HANDLE_EXCEPTIONS \
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do { \
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do { \
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double tmp, dummy; \
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double tmp, dummy; \
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if (_fex & FP_EX_INVALID) \
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if (_fex & FP_EX_INVALID) \
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{ \
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{ \
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tmp = 0.0; \
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tmp = 0.0; \
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__asm__ __volatile__ ("frcpa.s0 %0,p1=f0,f0" \
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__asm__ __volatile__ ("frcpa.s0 %0,p1=f0,f0" \
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: "=f" (tmp) : : "p1" ); \
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: "=f" (tmp) : : "p1" ); \
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} \
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} \
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if (_fex & FP_EX_DIVZERO) \
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if (_fex & FP_EX_DIVZERO) \
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{ \
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{ \
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__asm__ __volatile__ ("frcpa.s0 %0,p1=f1,f0" \
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__asm__ __volatile__ ("frcpa.s0 %0,p1=f1,f0" \
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: "=f" (tmp) : : "p1" ); \
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: "=f" (tmp) : : "p1" ); \
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} \
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} \
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if (_fex & FP_EX_OVERFLOW) \
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if (_fex & FP_EX_OVERFLOW) \
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{ \
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{ \
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dummy = __DBL_MAX__; \
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dummy = __DBL_MAX__; \
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__asm__ __volatile__ ("fadd.d.s0 %0=%1,%1" \
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__asm__ __volatile__ ("fadd.d.s0 %0=%1,%1" \
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: "=f" (dummy) : "0" (dummy)); \
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: "=f" (dummy) : "0" (dummy)); \
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} \
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} \
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if (_fex & FP_EX_UNDERFLOW) \
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if (_fex & FP_EX_UNDERFLOW) \
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{ \
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{ \
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dummy = __DBL_MIN__; \
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dummy = __DBL_MIN__; \
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__asm__ __volatile__ ("fnma.d.s0 %0=%1,%1,f0" \
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__asm__ __volatile__ ("fnma.d.s0 %0=%1,%1,f0" \
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: "=f" (tmp) : "f" (dummy)); \
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: "=f" (tmp) : "f" (dummy)); \
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} \
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} \
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if (_fex & FP_EX_INEXACT) \
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if (_fex & FP_EX_INEXACT) \
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{ \
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{ \
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dummy = __DBL_MAX__; \
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dummy = __DBL_MAX__; \
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__asm__ __volatile__ ("fsub.d.s0 %0=%1,f1" \
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__asm__ __volatile__ ("fsub.d.s0 %0=%1,f1" \
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: "=f" (dummy) : "0" (dummy)); \
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: "=f" (dummy) : "0" (dummy)); \
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} \
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} \
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} while (0)
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} while (0)
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#define FP_RND_NEAREST 0
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#define FP_RND_NEAREST 0
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#define FP_RND_ZERO 0xc00L
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#define FP_RND_ZERO 0xc00L
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#define FP_RND_PINF 0x800L
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#define FP_RND_PINF 0x800L
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#define FP_RND_MINF 0x400L
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#define FP_RND_MINF 0x400L
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#define _FP_DECL_EX \
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#define _FP_DECL_EX \
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unsigned long int _fpsr __attribute__ ((unused)) = FP_RND_NEAREST
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unsigned long int _fpsr __attribute__ ((unused)) = FP_RND_NEAREST
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#define FP_INIT_ROUNDMODE \
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#define FP_INIT_ROUNDMODE \
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do { \
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do { \
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__asm__ __volatile__ ("mov.m %0=ar.fpsr" \
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__asm__ __volatile__ ("mov.m %0=ar.fpsr" \
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: "=r" (_fpsr)); \
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: "=r" (_fpsr)); \
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} while (0)
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} while (0)
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#define FP_ROUNDMODE (_fpsr & 0xc00L)
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#define FP_ROUNDMODE (_fpsr & 0xc00L)
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#define __LITTLE_ENDIAN 1234
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#define __LITTLE_ENDIAN 1234
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#define __BIG_ENDIAN 4321
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#define __BIG_ENDIAN 4321
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#define __BYTE_ORDER __LITTLE_ENDIAN
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#define __BYTE_ORDER __LITTLE_ENDIAN
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/* Define ALIASNAME as a strong alias for NAME. */
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/* Define ALIASNAME as a strong alias for NAME. */
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#define strong_alias(name, aliasname) _strong_alias(name, aliasname)
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#define strong_alias(name, aliasname) _strong_alias(name, aliasname)
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#define _strong_alias(name, aliasname) \
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#define _strong_alias(name, aliasname) \
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extern __typeof (name) aliasname __attribute__ ((alias (#name)));
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extern __typeof (name) aliasname __attribute__ ((alias (#name)));
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