/* Definitions of target machine for GNU compiler for picoChip
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/* Definitions of target machine for GNU compiler for picoChip
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Copyright (C) 2001, 2008 Free Software Foundation, Inc.
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Copyright (C) 2001, 2008 Free Software Foundation, Inc.
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Contributed by picoChip Designs Ltd. (http://www.picochip.com)
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Contributed by picoChip Designs Ltd. (http://www.picochip.com)
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Maintained by Daniel Towner (daniel.towner@picochip.com) and
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Maintained by Daniel Towner (daniel.towner@picochip.com) and
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Hariharan Sandanagobalane (hariharan@picochip.com).
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Hariharan Sandanagobalane (hariharan@picochip.com).
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GCC is distributed in the hope that it will be useful,
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not, see
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along with GCC; see the file COPYING3. If not, see
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<http://www.gnu.org/licenses/>. */
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<http://www.gnu.org/licenses/>. */
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/* Which type of DFA scheduling to use - schedule for speed (VLIW), or
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/* Which type of DFA scheduling to use - schedule for speed (VLIW), or
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schedule for space. When scheduling for space, attempt to schedule
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schedule for space. When scheduling for space, attempt to schedule
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into stall cycles, but don't pack instructions. */
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into stall cycles, but don't pack instructions. */
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enum picochip_dfa_type
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enum picochip_dfa_type
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{
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{
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DFA_TYPE_NONE,
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DFA_TYPE_NONE,
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DFA_TYPE_SPACE,
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DFA_TYPE_SPACE,
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DFA_TYPE_SPEED
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DFA_TYPE_SPEED
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};
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};
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extern enum picochip_dfa_type picochip_schedule_type;
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extern enum picochip_dfa_type picochip_schedule_type;
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/* Controlling the Compilation Driver */
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/* Controlling the Compilation Driver */
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/* Pass through the save-temps command option. */
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/* Pass through the save-temps command option. */
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#define LINK_SPEC " %{save-temps:--save-temps}"
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#define LINK_SPEC " %{save-temps:--save-temps}"
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/* This is an embedded processor, and only supports a cut-down version of
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/* This is an embedded processor, and only supports a cut-down version of
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* the standard C library. */
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* the standard C library. */
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#define LIB_SPEC "-lpicoC"
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#define LIB_SPEC "-lpicoC"
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/* The start file is automatically provided by the linker. */
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/* The start file is automatically provided by the linker. */
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#define STARTFILE_SPEC ""
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#define STARTFILE_SPEC ""
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/* Run-time Target Specification */
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/* Run-time Target Specification */
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/* Define some additional pre-processor macros. */
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/* Define some additional pre-processor macros. */
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#define TARGET_CPU_CPP_BUILTINS() \
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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do \
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{ \
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{ \
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builtin_define ("NO_TRAMPOLINES"); \
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builtin_define ("NO_TRAMPOLINES"); \
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builtin_define ("PICOCHIP"); \
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builtin_define ("PICOCHIP"); \
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builtin_define ("__PICOCHIP__"); \
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builtin_define ("__PICOCHIP__"); \
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} \
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} \
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while (0)
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while (0)
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/* Translate requests for particular AEs into their respective ISA
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/* Translate requests for particular AEs into their respective ISA
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options. Note that byte access is enabled by default. */
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options. Note that byte access is enabled by default. */
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#define TARGET_OPTION_TRANSLATE_TABLE \
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#define TARGET_OPTION_TRANSLATE_TABLE \
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{ "-mae=ANY", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=ANY", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=ANY2", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=ANY2", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=ANY3", "-mmul-type=none" }, \
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{ "-mae=ANY3", "-mmul-type=none" }, \
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{ "-mae=STAN", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=STAN", "-mmul-type=none -mno-byte-access" }, \
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{ "-mae=STAN2", "-mmul-type=mac -mno-byte-access" }, \
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{ "-mae=STAN2", "-mmul-type=mac -mno-byte-access" }, \
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{ "-mae=STAN3", "-mmul-type=mac " }, \
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{ "-mae=STAN3", "-mmul-type=mac " }, \
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{ "-mae=MAC", "-mmul-type=mac -mno-byte-access" }, \
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{ "-mae=MAC", "-mmul-type=mac -mno-byte-access" }, \
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{ "-mae=MUL", "-mmul-type=mul" }, \
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{ "-mae=MUL", "-mmul-type=mul" }, \
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{ "-mae=MEM", "-mmul-type=mul" }, \
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{ "-mae=MEM", "-mmul-type=mul" }, \
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{ "-mae=MEM2", "-mmul-type=mul" }, \
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{ "-mae=MEM2", "-mmul-type=mul" }, \
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{ "-mae=CTRL", "-mmul-type=mul" }, \
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{ "-mae=CTRL", "-mmul-type=mul" }, \
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{ "-mae=CTRL2", "-mmul-type=mul" }
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{ "-mae=CTRL2", "-mmul-type=mul" }
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/* Specify the default options, so that the multilib build doesn't
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/* Specify the default options, so that the multilib build doesn't
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need to provide special cases for the defaults. */
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need to provide special cases for the defaults. */
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#define MULTILIB_DEFAULTS \
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#define MULTILIB_DEFAULTS \
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{ "mmul-type=mul", "mbyte-access"}
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{ "mmul-type=mul", "mbyte-access"}
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#define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
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#define TARGET_HAS_BYTE_ACCESS (picochip_has_byte_access)
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#define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
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#define TARGET_HAS_MUL_UNIT (picochip_has_mul_unit)
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#define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
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#define TARGET_HAS_MAC_UNIT (picochip_has_mac_unit)
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#define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
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#define TARGET_HAS_MULTIPLY (picochip_has_mac_unit || picochip_has_mul_unit)
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/* Allow some options to be overriden. In particular, the 2nd
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/* Allow some options to be overriden. In particular, the 2nd
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scheduling pass option is switched off, and a machine dependent
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scheduling pass option is switched off, and a machine dependent
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reorganisation ensures that it is run later on, after the second
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reorganisation ensures that it is run later on, after the second
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jump optimisation. */
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jump optimisation. */
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#define OVERRIDE_OPTIONS picochip_override_options()
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#define OVERRIDE_OPTIONS picochip_override_options()
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#define CAN_DEBUG_WITHOUT_FP 1
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#define CAN_DEBUG_WITHOUT_FP 1
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#define TARGET_VERSION fprintf(stderr, "(picoChip)");
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#define TARGET_VERSION fprintf(stderr, "(picoChip)");
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/* Storage Layout */
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/* Storage Layout */
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/* picoChip processors are 16-bit machines, little endian. */
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/* picoChip processors are 16-bit machines, little endian. */
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#define BITS_BIG_ENDIAN 0
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define BITS_PER_UNIT 8
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#define BITS_PER_UNIT 8
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#define BITS_PER_WORD 16
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#define BITS_PER_WORD 16
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#define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
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#define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
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#define POINTER_SIZE BITS_PER_WORD
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#define POINTER_SIZE BITS_PER_WORD
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/* Promote those modes that are smaller than an int, to int mode. */
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/* Promote those modes that are smaller than an int, to int mode. */
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#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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((GET_MODE_CLASS (MODE) == MODE_INT \
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((GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
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&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
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? (MODE) = HImode : 0)
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? (MODE) = HImode : 0)
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/* All parameters are at least this aligned. Parameters are passed
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/* All parameters are at least this aligned. Parameters are passed
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one-per-register. */
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one-per-register. */
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#define PARM_BOUNDARY BITS_PER_WORD
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#define PARM_BOUNDARY BITS_PER_WORD
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/* The main stack pointer is guaranteed to be aligned to the most
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/* The main stack pointer is guaranteed to be aligned to the most
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strict data alignment. */
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strict data alignment. */
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#define STACK_BOUNDARY 32
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#define STACK_BOUNDARY 32
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/* Function entry point is byte aligned. */
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/* Function entry point is byte aligned. */
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#define FUNCTION_BOUNDARY 8
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#define FUNCTION_BOUNDARY 8
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/* This is the biggest alignment that can be allowed on this machine.
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/* This is the biggest alignment that can be allowed on this machine.
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Since the STANs have only 256 byte memory, it doesnt make sense
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Since the STANs have only 256 byte memory, it doesnt make sense
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to have alignments greater than 32 bytes. Hence the value */
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to have alignments greater than 32 bytes. Hence the value */
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#define MAX_OFILE_ALIGNMENT 32*8
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#define MAX_OFILE_ALIGNMENT 32*8
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/* The strictest data object alignment, which repesents a register pair. */
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/* The strictest data object alignment, which repesents a register pair. */
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#define BIGGEST_ALIGNMENT 32
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#define BIGGEST_ALIGNMENT 32
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/* The hardware doesn't allow unaligned memory access. */
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/* The hardware doesn't allow unaligned memory access. */
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#define STRICT_ALIGNMENT 1
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#define STRICT_ALIGNMENT 1
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/* We want the 'unix' style bitfield packing algorithm. */
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/* We want the 'unix' style bitfield packing algorithm. */
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#define PCC_BITFIELD_TYPE_MATTERS 1
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#define PCC_BITFIELD_TYPE_MATTERS 1
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/* Support up to 64-bit integers. */
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/* Support up to 64-bit integers. */
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#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
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#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
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/* We don't support floating point, but give it a sensible definition. */
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/* We don't support floating point, but give it a sensible definition. */
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#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
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#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
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/* Layout of Source Language Data Types. */
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/* Layout of Source Language Data Types. */
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#define INT_TYPE_SIZE BITS_PER_WORD
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#define INT_TYPE_SIZE BITS_PER_WORD
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/* The normal sizes for C scalar data. */
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/* The normal sizes for C scalar data. */
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#define CHAR_TYPE_SIZE 8
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#define CHAR_TYPE_SIZE 8
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#define SHORT_TYPE_SIZE 16
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#define SHORT_TYPE_SIZE 16
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#define LONG_TYPE_SIZE 32
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#define LONG_TYPE_SIZE 32
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#define LONG_LONG_TYPE_SIZE 64
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#define LONG_LONG_TYPE_SIZE 64
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/* We don't support the following data types, but still give them
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/* We don't support the following data types, but still give them
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sensible values. */
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sensible values. */
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#define FLOAT_TYPE_SIZE 32
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 32
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#define LONG_DOUBLE_TYPE_SIZE 32
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#define LONG_DOUBLE_TYPE_SIZE 32
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/* Plain `char' is a signed type, since the hardware sign-extends
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/* Plain `char' is a signed type, since the hardware sign-extends
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bytes when loading them from memory into a register. */
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bytes when loading them from memory into a register. */
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#define DEFAULT_SIGNED_CHAR 1
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#define DEFAULT_SIGNED_CHAR 1
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/* Note that the names of the types used in the following macros must
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/* Note that the names of the types used in the following macros must
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be precisely the same as those defined internally in gcc. For
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be precisely the same as those defined internally in gcc. For
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example, `unsigned short' wouldn't work as a type string, since gcc
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example, `unsigned short' wouldn't work as a type string, since gcc
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doesn't define any type with this exact string. The correct string
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doesn't define any type with this exact string. The correct string
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to use is `short unsigned int'. */
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to use is `short unsigned int'. */
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#define SIZE_TYPE "unsigned int"
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#define SIZE_TYPE "unsigned int"
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#define PTRDIFF_TYPE "int"
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#define PTRDIFF_TYPE "int"
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#define WCHAR_TYPE "short unsigned int"
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#define WCHAR_TYPE "short unsigned int"
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#define WCHAR_TYPE_SIZE 16
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#define WCHAR_TYPE_SIZE 16
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#define WINT_TYPE "unsigned int"
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#define WINT_TYPE "unsigned int"
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/* Register Usage */
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/* Register Usage */
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/* Picochip has 16 16-bit registers, a condition code register and an
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/* Picochip has 16 16-bit registers, a condition code register and an
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(inaccessible) instruction pointer. One of these registers (r15) is
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(inaccessible) instruction pointer. One of these registers (r15) is
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special, and is either used to load a constant anywhere a register
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special, and is either used to load a constant anywhere a register
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can normally be used, or is used to specify a dummy destination
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can normally be used, or is used to specify a dummy destination
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(e.g., when setting condition flags). We also define some pseudo
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(e.g., when setting condition flags). We also define some pseudo
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registers to represent condition codes, the frame pointer and the
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registers to represent condition codes, the frame pointer and the
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argument pointer. The latter two are eliminated wherever possible.
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argument pointer. The latter two are eliminated wherever possible.
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Pairs of general registers may be combined to form 32-bit registers.
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Pairs of general registers may be combined to form 32-bit registers.
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The picoChip registers are as follows:
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The picoChip registers are as follows:
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0..1 - function return value
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0..1 - function return value
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0..5 - first 6 function parameters
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0..5 - first 6 function parameters
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6..11 - General purpose
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6..11 - General purpose
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12 - link register
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12 - link register
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13 - stack pointer
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13 - stack pointer
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14 - specialized pointer
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14 - specialized pointer
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15 - long constant or /dev/null
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15 - long constant or /dev/null
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(16) acc0
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(16) acc0
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(17) pseudo condition code
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(17) pseudo condition code
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(18) pseudo frame pointer
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(18) pseudo frame pointer
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(19) pseudo arg pointer
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(19) pseudo arg pointer
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Registers 0..6, 12, 13, 14, 15 are caller save
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Registers 0..6, 12, 13, 14, 15 are caller save
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Registers 0..12, 14 are available to the register allocator.
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Registers 0..12, 14 are available to the register allocator.
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In addition, the DSP variant of the ISA allows extra accumulator
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In addition, the DSP variant of the ISA allows extra accumulator
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registers to be accessed. These are special purpose registers,
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registers to be accessed. These are special purpose registers,
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which are not currently used by the compiler.
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which are not currently used by the compiler.
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*/
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*/
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/* Basic Characteristics of Registers */
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/* Basic Characteristics of Registers */
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/* We have 16 hard registers plus 3 pseudo hard registers and an accumulator. */
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/* We have 16 hard registers plus 3 pseudo hard registers and an accumulator. */
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#define FIRST_PSEUDO_REGISTER 20
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#define FIRST_PSEUDO_REGISTER 20
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/* The first non-hard register. Only used internally by the picoChip port. */
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/* The first non-hard register. Only used internally by the picoChip port. */
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#define FIRST_NONHARD_REGISTER 18
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#define FIRST_NONHARD_REGISTER 18
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/* Cannot use SP, CST, CC, FP, AP */
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/* Cannot use SP, CST, CC, FP, AP */
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#define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
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#define FIXED_REGISTERS {0,0,0,0,0,0,0,0, 0,0,0,0,0,1,0,1, 1,1,1,1}
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/* Those that are clobbered by a function call (includes pseudo-regs) */
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/* Those that are clobbered by a function call (includes pseudo-regs) */
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#define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
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#define CALL_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,1, 1,1,1,1}
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#define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
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#define CALL_REALLY_USED_REGISTERS {1,1,1,1,1,1,0,0, 0,0,0,0,1,1,0,0, 0,1,0,0}
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/* Define the number of the picoChip link and condition psuedo registers. */
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/* Define the number of the picoChip link and condition psuedo registers. */
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#define LINK_REGNUM 12
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#define LINK_REGNUM 12
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#define CC_REGNUM 17
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#define CC_REGNUM 17
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#define ACC_REGNUM 16
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#define ACC_REGNUM 16
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/* Order of Allocation of Registers */
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/* Order of Allocation of Registers */
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/* The registers are allocated starting with the caller-clobbered
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/* The registers are allocated starting with the caller-clobbered
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registers, in reverse order. The registers are then listed in an
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registers, in reverse order. The registers are then listed in an
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order which means that they are efficiently saved in pairs (i.e.,
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order which means that they are efficiently saved in pairs (i.e.,
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one 32-bit store can be used instead of two 16-bit stores to save
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one 32-bit store can be used instead of two 16-bit stores to save
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the registers into the stack). The exception to this is the use of
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the registers into the stack). The exception to this is the use of
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r14 (AP) register, which also appears early on. This is because the
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r14 (AP) register, which also appears early on. This is because the
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AP register can be used to encode memory operations more
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AP register can be used to encode memory operations more
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efficiently than other registers. Some code can be made more
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efficiently than other registers. Some code can be made more
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compact as a result. */
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compact as a result. */
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/* My current feeling is that r14 should go to the end and maybe even r12.
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/* My current feeling is that r14 should go to the end and maybe even r12.
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It seems like the overhead of store/load that will occur since we cant
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It seems like the overhead of store/load that will occur since we cant
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pair anything up with r14 will be higher than the advantage of smaller
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pair anything up with r14 will be higher than the advantage of smaller
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encoding.
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encoding.
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Also r12 is put towards the end for leaf functions. Since leaf functions
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Also r12 is put towards the end for leaf functions. Since leaf functions
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do not have any calls, the prologue/epilogue for them wouldnt save up/
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do not have any calls, the prologue/epilogue for them wouldnt save up/
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restore its value. So, it doesnt make sense for us to use it in the middle,
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restore its value. So, it doesnt make sense for us to use it in the middle,
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if we can avoid it. */
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if we can avoid it. */
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#define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
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#define REG_ALLOC_ORDER {5,4,3,2,1,0,12,6,7,8,9,10,11,14,16,0,0,0,0,0}
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#define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
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#define LEAF_REG_ALLOC_ORDER {5,4,3,2,1,0,6,7,8,9,10,11,14,12,16,0,0,0,0,0}
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|
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/* We can dynamically change the REG_ALLOC_ORDER using the following hook.
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/* We can dynamically change the REG_ALLOC_ORDER using the following hook.
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It would be desirable to change it for leaf functions so we can put
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It would be desirable to change it for leaf functions so we can put
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r12 at the end of this list.*/
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r12 at the end of this list.*/
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#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc ()
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#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc ()
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/* How Values Fit in Registers */
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/* How Values Fit in Registers */
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|
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/* Number of consecutive hard regs needed starting at reg REGNO
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/* Number of consecutive hard regs needed starting at reg REGNO
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to hold something of mode MODE. */
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to hold something of mode MODE. */
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#define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
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#define HARD_REGNO_NREGS(REGNO, MODE) picochip_regno_nregs((REGNO), (MODE))
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|
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/* Is it ok to place MODE in REGNO? Require that the register number
|
/* Is it ok to place MODE in REGNO? Require that the register number
|
be aligned. */
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be aligned. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
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#define HARD_REGNO_MODE_OK(REGNO, MODE) picochip_hard_regno_mode_ok(REGNO, MODE)
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|
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#define MODES_TIEABLE_P(MODE1,MODE2) 1
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#define MODES_TIEABLE_P(MODE1,MODE2) 1
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|
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/* Don't copy the cc register ('cos you can't put it back). */
|
/* Don't copy the cc register ('cos you can't put it back). */
|
#define AVOID_CCMODE_COPIES 1
|
#define AVOID_CCMODE_COPIES 1
|
|
|
/* Register Classes */
|
/* Register Classes */
|
|
|
enum reg_class
|
enum reg_class
|
{
|
{
|
NO_REGS, /* no registers in set */
|
NO_REGS, /* no registers in set */
|
FRAME_REGS, /* registers with a long offset */
|
FRAME_REGS, /* registers with a long offset */
|
PTR_REGS, /* registers without an offset */
|
PTR_REGS, /* registers without an offset */
|
CONST_REGS, /* registers for long constants */
|
CONST_REGS, /* registers for long constants */
|
NULL_REGS, /* registers which ignore writes */
|
NULL_REGS, /* registers which ignore writes */
|
CC_REGS, /* condition code registers */
|
CC_REGS, /* condition code registers */
|
ACC_REGS, /* Accumulator registers */
|
ACC_REGS, /* Accumulator registers */
|
TWIN_REGS, /* registers which can be paired */
|
TWIN_REGS, /* registers which can be paired */
|
GR_REGS, /* general purpose registers */
|
GR_REGS, /* general purpose registers */
|
ALL_REGS, /* all registers */
|
ALL_REGS, /* all registers */
|
LIM_REG_CLASSES, /* max value + 1 */
|
LIM_REG_CLASSES, /* max value + 1 */
|
|
|
/* Some aliases */
|
/* Some aliases */
|
GENERAL_REGS = GR_REGS
|
GENERAL_REGS = GR_REGS
|
};
|
};
|
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
|
|
/* The following macro defines cover classes for Integrated Register
|
/* The following macro defines cover classes for Integrated Register
|
Allocator. Cover classes is a set of non-intersected register
|
Allocator. Cover classes is a set of non-intersected register
|
classes covering all hard registers used for register allocation
|
classes covering all hard registers used for register allocation
|
purpose. Any move between two registers of a cover class should be
|
purpose. Any move between two registers of a cover class should be
|
cheaper than load or store of the registers. The macro value is
|
cheaper than load or store of the registers. The macro value is
|
array of register classes with LIM_REG_CLASSES used as the end
|
array of register classes with LIM_REG_CLASSES used as the end
|
marker. */
|
marker. */
|
|
|
#define IRA_COVER_CLASSES \
|
#define IRA_COVER_CLASSES \
|
{ \
|
{ \
|
GR_REGS, LIM_REG_CLASSES \
|
GR_REGS, LIM_REG_CLASSES \
|
}
|
}
|
|
|
|
|
/* The names of the register classes */
|
/* The names of the register classes */
|
#define REG_CLASS_NAMES \
|
#define REG_CLASS_NAMES \
|
{ \
|
{ \
|
"NO_REGS", \
|
"NO_REGS", \
|
"FRAME_REGS", \
|
"FRAME_REGS", \
|
"PTR_REGS", \
|
"PTR_REGS", \
|
"CONST_REGS", \
|
"CONST_REGS", \
|
"NULL_REGS", \
|
"NULL_REGS", \
|
"CC_REGS", \
|
"CC_REGS", \
|
"ACC_REGS", \
|
"ACC_REGS", \
|
"TWIN_REGS", \
|
"TWIN_REGS", \
|
"GR_REGS", \
|
"GR_REGS", \
|
"ALL_REGS" \
|
"ALL_REGS" \
|
}
|
}
|
|
|
/* Each reg class is an array of 32-bit integers. Each array must be
|
/* Each reg class is an array of 32-bit integers. Each array must be
|
long enough to store one bit for every pseudo register. Thus in the
|
long enough to store one bit for every pseudo register. Thus in the
|
following code, each array only stores one 32-bit value. */
|
following code, each array only stores one 32-bit value. */
|
#define REG_CLASS_CONTENTS \
|
#define REG_CLASS_CONTENTS \
|
{ \
|
{ \
|
{0x00000000}, /* no registers */ \
|
{0x00000000}, /* no registers */ \
|
{0x00002000}, /* frame */ \
|
{0x00002000}, /* frame */ \
|
{0x00004000}, /* pointer */ \
|
{0x00004000}, /* pointer */ \
|
{0x00008000}, /* const */ \
|
{0x00008000}, /* const */ \
|
{0x00008000}, /* null */ \
|
{0x00008000}, /* null */ \
|
{0x00020000}, /* cc */ \
|
{0x00020000}, /* cc */ \
|
{0x00010000}, /* acc0 */ \
|
{0x00010000}, /* acc0 */ \
|
{0x00000FFF}, /* twin */ \
|
{0x00000FFF}, /* twin */ \
|
{0x000CFFFF}, /* general registers - includes pseudo-arg */ \
|
{0x000CFFFF}, /* general registers - includes pseudo-arg */ \
|
{0x000FFFFF} /* all registers - includes pseudo-arg */ \
|
{0x000FFFFF} /* all registers - includes pseudo-arg */ \
|
}
|
}
|
|
|
/* The earliest register class containing the given register. */
|
/* The earliest register class containing the given register. */
|
extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
|
extern const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER];
|
#define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
|
#define REGNO_REG_CLASS(REGNO) picochip_regno_reg_class[REGNO]
|
|
|
/* Any register can be a base pointer. */
|
/* Any register can be a base pointer. */
|
#define BASE_REG_CLASS GR_REGS
|
#define BASE_REG_CLASS GR_REGS
|
|
|
/* Any register can be an index. */
|
/* Any register can be an index. */
|
#define INDEX_REG_CLASS GR_REGS
|
#define INDEX_REG_CLASS GR_REGS
|
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
(REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
|
(REGNO_REG_CLASS (REGNO) != CC_REGS && REGNO_REG_CLASS (REGNO) != ACC_REGS)
|
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
|
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
|
|
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
|
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
|
#define CLASS_MAX_NREGS(CLASS, MODE) picochip_class_max_nregs(CLASS, MODE)
|
|
|
|
|
/* Stack Layout and Calling Conventions */
|
/* Stack Layout and Calling Conventions */
|
|
|
#define STACK_GROWS_DOWNWARD 1
|
#define STACK_GROWS_DOWNWARD 1
|
|
|
/* The frame pointer points to the outgoing argument area, so the
|
/* The frame pointer points to the outgoing argument area, so the
|
locals are above that. */
|
locals are above that. */
|
#define STARTING_FRAME_OFFSET 0
|
#define STARTING_FRAME_OFFSET 0
|
|
|
#define FIRST_PARM_OFFSET(FNDECL) 0
|
#define FIRST_PARM_OFFSET(FNDECL) 0
|
|
|
/* Specify where the return address lives before entry to the
|
/* Specify where the return address lives before entry to the
|
prologue. This is required to enable DWARF debug information to be
|
prologue. This is required to enable DWARF debug information to be
|
generated. */
|
generated. */
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
|
|
|
#define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
|
#define RETURN_ADDR_RTX(count,frameaddr) picochip_return_addr_rtx(count,frameaddr)
|
|
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
|
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGNUM)
|
|
|
/* Registers that Address the Stack Frame */
|
/* Registers that Address the Stack Frame */
|
|
|
#define STACK_POINTER_REGNUM 13
|
#define STACK_POINTER_REGNUM 13
|
#define FRAME_POINTER_REGNUM 18
|
#define FRAME_POINTER_REGNUM 18
|
#define ARG_POINTER_REGNUM 19
|
#define ARG_POINTER_REGNUM 19
|
|
|
/* Eliminating Frame Pointer and Arg Pointer. The frame and argument
|
/* Eliminating Frame Pointer and Arg Pointer. The frame and argument
|
pointers are eliminated wherever possible, by replacing them with
|
pointers are eliminated wherever possible, by replacing them with
|
offsets from the stack pointer. */
|
offsets from the stack pointer. */
|
|
|
#define ELIMINABLE_REGS \
|
#define ELIMINABLE_REGS \
|
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
|
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
|
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
|
#define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
|
OFFSET = initial_elimination_offset(FROM, TO);
|
OFFSET = initial_elimination_offset(FROM, TO);
|
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
|
|
#define PUSH_ARGS 0
|
#define PUSH_ARGS 0
|
|
|
/* Functions don't pop their args. */
|
/* Functions don't pop their args. */
|
#define RETURN_POPS_ARGS(FNDECL, FNTYPE, STACK) 0
|
#define RETURN_POPS_ARGS(FNDECL, FNTYPE, STACK) 0
|
|
|
/* Passing Arguments in Registers */
|
/* Passing Arguments in Registers */
|
|
|
/* Store the offset of the next argument. */
|
/* Store the offset of the next argument. */
|
#define CUMULATIVE_ARGS unsigned
|
#define CUMULATIVE_ARGS unsigned
|
|
|
/* Decide how function arguments are handled. */
|
/* Decide how function arguments are handled. */
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
picochip_function_arg (CUM, MODE, TYPE, NAMED)
|
picochip_function_arg (CUM, MODE, TYPE, NAMED)
|
|
|
/* Incoming arguments are always the same as normal arguments, except
|
/* Incoming arguments are always the same as normal arguments, except
|
for a function which uses variadic arguments, in which case all
|
for a function which uses variadic arguments, in which case all
|
arguments are effectively passed on the stack. */
|
arguments are effectively passed on the stack. */
|
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
|
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
|
picochip_incoming_function_arg(CUM, MODE, TYPE, NAMED)
|
picochip_incoming_function_arg(CUM, MODE, TYPE, NAMED)
|
|
|
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
|
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
|
((CUM) = 0)
|
((CUM) = 0)
|
|
|
#define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
|
#define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
|
(CUM) = picochip_arg_advance (CUM, MODE, TYPE, NAMED)
|
(CUM) = picochip_arg_advance (CUM, MODE, TYPE, NAMED)
|
|
|
/* Originally this used TYPE_ALIGN to determine the
|
/* Originally this used TYPE_ALIGN to determine the
|
alignment. Unfortunately, this fails in some cases, because the
|
alignment. Unfortunately, this fails in some cases, because the
|
type is unknown (e.g., libcall's). Instead, use GET_MODE_ALIGNMENT
|
type is unknown (e.g., libcall's). Instead, use GET_MODE_ALIGNMENT
|
since the mode is always present. */
|
since the mode is always present. */
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
|
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
|
picochip_get_function_arg_boundary(MODE)
|
picochip_get_function_arg_boundary(MODE)
|
|
|
/* The first 6 registers can hold parameters. */
|
/* The first 6 registers can hold parameters. */
|
#define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
|
#define FUNCTION_ARG_REGNO_P(REGNO) ((REGNO) < 6)
|
|
|
/* How Scalar Function Values are Returned
|
/* How Scalar Function Values are Returned
|
Do we need this?? */
|
Do we need this?? */
|
#define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
|
#define FUNCTION_VALUE(VALTYPE,FUNC) picochip_function_value(VALTYPE, FUNC, 0)
|
|
|
#define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
|
#define LIBCALL_VALUE(MODE) (gen_rtx_REG (MODE, 0))
|
|
|
/* Results are in register zero. If an SImode register is returned,
|
/* Results are in register zero. If an SImode register is returned,
|
reg0 will suffice to mean R[0:1]. */
|
reg0 will suffice to mean R[0:1]. */
|
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
|
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
|
|
|
/* Don't automatically pass struct's in memory - use the
|
/* Don't automatically pass struct's in memory - use the
|
* RETURN_IN_MEMORY macro to determine when structs are returned in
|
* RETURN_IN_MEMORY macro to determine when structs are returned in
|
* memory, and when in registers. */
|
* memory, and when in registers. */
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
/* Function Entry and Exit */
|
/* Function Entry and Exit */
|
|
|
/* The epilogue doesn't clobber anything. */
|
/* The epilogue doesn't clobber anything. */
|
#define EPILOGUE_USES(REGNO) 0
|
#define EPILOGUE_USES(REGNO) 0
|
|
|
/* Generating Code for Profiling. No profiling implemented */
|
/* Generating Code for Profiling. No profiling implemented */
|
|
|
#define FUNCTION_PROFILER(FILE,LABELNO)
|
#define FUNCTION_PROFILER(FILE,LABELNO)
|
|
|
/* Trampolines for Nested Functions */
|
/* Trampolines for Nested Functions */
|
|
|
/* No trampolines. */
|
/* No trampolines. */
|
#define TRAMPOLINE_SIZE 0
|
#define TRAMPOLINE_SIZE 0
|
|
|
/* Addressing Modes */
|
/* Addressing Modes */
|
|
|
#define MAX_REGS_PER_ADDRESS 1
|
#define MAX_REGS_PER_ADDRESS 1
|
|
|
/* Legitimize reload address tries machine dependent means of
|
/* Legitimize reload address tries machine dependent means of
|
reloading addresses. There seems to be a strange error in gcc,
|
reloading addresses. There seems to be a strange error in gcc,
|
which necessitates this macro. Consider:
|
which necessitates this macro. Consider:
|
|
|
set (reg A) (symbol_ref)
|
set (reg A) (symbol_ref)
|
set (reg B) (plus (reg A) (const_int))
|
set (reg B) (plus (reg A) (const_int))
|
|
|
A symbol_ref is a valid constant, so the symbol_ref is propagated
|
A symbol_ref is a valid constant, so the symbol_ref is propagated
|
into the second instruction to generate the instruction:
|
into the second instruction to generate the instruction:
|
|
|
set (reg B) (plus (symbol_ref) (const_int))
|
set (reg B) (plus (symbol_ref) (const_int))
|
|
|
This is an invalid address, and find_reloads_address correctly
|
This is an invalid address, and find_reloads_address correctly
|
determines this. However, that function doesn't generate a valid
|
determines this. However, that function doesn't generate a valid
|
replacement for the now invalid address, and the invalid address is
|
replacement for the now invalid address, and the invalid address is
|
output into the assembly language. To fix the problem without
|
output into the assembly language. To fix the problem without
|
changing gcc itself, the following macro tests when such an invalid
|
changing gcc itself, the following macro tests when such an invalid
|
address has been computed, and wraps it up inside a constant rtx. A
|
address has been computed, and wraps it up inside a constant rtx. A
|
constant rtx can be correctly reloaded by the function, and hence
|
constant rtx can be correctly reloaded by the function, and hence
|
correct code is generated. */
|
correct code is generated. */
|
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
if (picochip_symbol_offset(X)) { X = gen_rtx_CONST(MODE, X); }
|
if (picochip_symbol_offset(X)) { X = gen_rtx_CONST(MODE, X); }
|
|
|
/* Nonzero if the constant rtx X is a legitimate general operand. X
|
/* Nonzero if the constant rtx X is a legitimate general operand. X
|
satisfies CONSTANT_P. */
|
satisfies CONSTANT_P. */
|
|
|
#define LEGITIMATE_CONSTANT_P(X) 1
|
#define LEGITIMATE_CONSTANT_P(X) 1
|
|
|
|
|
/* Condition Code Status */
|
/* Condition Code Status */
|
|
|
#define CC_STATUS_MDEP unsigned
|
#define CC_STATUS_MDEP unsigned
|
#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
|
#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
|
|
|
/* Describing Relative Costs of Operations */
|
/* Describing Relative Costs of Operations */
|
|
|
/* Bytes are no faster than words. */
|
/* Bytes are no faster than words. */
|
#define SLOW_BYTE_ACCESS 1
|
#define SLOW_BYTE_ACCESS 1
|
|
|
/* The assembler is often able to optimise function call branches, so
|
/* The assembler is often able to optimise function call branches, so
|
don't try to CSE them in the compiler. This was the thinking before.
|
don't try to CSE them in the compiler. This was the thinking before.
|
But now, we realise that the benefits from CSE would mostly outweigh
|
But now, we realise that the benefits from CSE would mostly outweigh
|
the disadvantages. */
|
the disadvantages. */
|
#define NO_FUNCTION_CSE
|
#define NO_FUNCTION_CSE
|
|
|
|
|
/* Dividing the Output into Sections */
|
/* Dividing the Output into Sections */
|
|
|
#define TEXT_SECTION_ASM_OP ".section .text\n"
|
#define TEXT_SECTION_ASM_OP ".section .text\n"
|
#define DATA_SECTION_ASM_OP ".section .data\n"
|
#define DATA_SECTION_ASM_OP ".section .data\n"
|
#define BSS_SECTION_ASM_OP ".section .bss\n"
|
#define BSS_SECTION_ASM_OP ".section .bss\n"
|
/* picoChip is Harvard (separate data/instruction memories), so
|
/* picoChip is Harvard (separate data/instruction memories), so
|
read-only data must go into the data section. */
|
read-only data must go into the data section. */
|
#define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
|
#define READONLY_DATA_SECTION_ASM_OP ".section .data\n"
|
|
|
/* Defining the Output Assembler Language */
|
/* Defining the Output Assembler Language */
|
|
|
/* The Overall Framework of an Assembler File */
|
/* The Overall Framework of an Assembler File */
|
|
|
#define ASM_FILE_COMMENT "// "
|
#define ASM_FILE_COMMENT "// "
|
|
|
#define ASM_APP_ON "// High-level ASM start\n"
|
#define ASM_APP_ON "// High-level ASM start\n"
|
#define ASM_APP_OFF "// High-level ASM end\n"
|
#define ASM_APP_OFF "// High-level ASM end\n"
|
|
|
#define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING)
|
#define ASM_OUTPUT_IDENT(STREAM,STRING) fprintf(STREAM, ".ident %s\n", STRING)
|
|
|
/* Output of Data */
|
/* Output of Data */
|
|
|
#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
|
#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) picochip_output_ascii(FILE, PTR, LEN);
|
|
|
/* Output of Uninitialized Variables */
|
/* Output of Uninitialized Variables */
|
#define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
|
#define ASM_OUTPUT_ALIGNED_COMMON(FILE,NAME,SIZE,ALIGN) \
|
picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
|
picochip_output_aligned_common(FILE, NAME, SIZE, ALIGN)
|
|
|
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
|
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \
|
picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
|
picochip_output_aligned_local(FILE, NAME, SIZE, ALIGN)
|
|
|
/* Output and Generation of Labels */
|
/* Output and Generation of Labels */
|
|
|
#define ASM_OUTPUT_LABEL(STREAM,NAME) \
|
#define ASM_OUTPUT_LABEL(STREAM,NAME) \
|
do { picochip_output_label(STREAM, NAME); } while (0);
|
do { picochip_output_label(STREAM, NAME); } while (0);
|
|
|
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
|
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
|
{ picochip_output_labelref(STREAM, NAME); }
|
{ picochip_output_labelref(STREAM, NAME); }
|
|
|
/* Format must match that of picochip_output_label. */
|
/* Format must match that of picochip_output_label. */
|
#define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
|
#define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
|
picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
|
picochip_generate_internal_label(STRING,PREFIX,(long)NUM)
|
|
|
#define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
|
#define ASM_WEAKEN_LABEL(STREAM,NAME) picochip_weaken_label(STREAM,NAME);
|
|
|
/* Store in OUTPUT a string (made with alloca) containing an
|
/* Store in OUTPUT a string (made with alloca) containing an
|
assembler-name for a local static variable named NAME. LABELNO is
|
assembler-name for a local static variable named NAME. LABELNO is
|
an integer which is different for each call. The assembler can't
|
an integer which is different for each call. The assembler can't
|
use periods to generate the name, so we use a ___ separator
|
use periods to generate the name, so we use a ___ separator
|
instead. */
|
instead. */
|
|
|
#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
|
#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
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( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15), \
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( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 15), \
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sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
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sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
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|
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/* Macros Controlling Initialization Routines */
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/* Macros Controlling Initialization Routines */
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/* By defining this, the main function won't try to call `__main'. */
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/* By defining this, the main function won't try to call `__main'. */
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#define HAS_INIT_SECTION
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#define HAS_INIT_SECTION
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/* Output of Assembler Instructions */
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/* Output of Assembler Instructions */
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#define REGISTER_NAMES \
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#define REGISTER_NAMES \
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{"R0", "R1", "R2", "R3", \
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{"R0", "R1", "R2", "R3", \
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"R4", "R5", "R6", "R7", \
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"R4", "R5", "R6", "R7", \
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"R8", "R9", "R10", "R11", \
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"R8", "R9", "R10", "R11", \
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"R12", "FP", "R14", "R15", \
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"R12", "FP", "R14", "R15", \
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"acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
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"acc0", "pseudoCC", "pseudoFP", "pseudoAP"}
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|
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#define ADDITIONAL_REGISTER_NAMES \
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#define ADDITIONAL_REGISTER_NAMES \
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{ \
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{ \
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{ "R0", 0}, \
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{ "R0", 0}, \
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{ "R1", 1}, \
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{ "R1", 1}, \
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{ "R2", 2}, \
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{ "R2", 2}, \
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{ "R3", 3}, \
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{ "R3", 3}, \
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{ "R4", 4}, \
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{ "R4", 4}, \
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{ "R5", 5}, \
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{ "R5", 5}, \
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{ "R6", 6}, \
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{ "R6", 6}, \
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{ "R7", 7}, \
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{ "R7", 7}, \
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{ "R8", 8}, \
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{ "R8", 8}, \
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{ "R9", 9}, \
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{ "R9", 9}, \
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{ "R10", 10}, \
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{ "R10", 10}, \
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{ "R11", 11}, \
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{ "R11", 11}, \
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{ "R12", 12}, \
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{ "R12", 12}, \
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{ "FP", 13}, \
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{ "FP", 13}, \
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{ "R14", 14}, \
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{ "R14", 14}, \
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{ "R15", 15}, \
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{ "R15", 15}, \
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{ "acc0", 16}, \
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{ "acc0", 16}, \
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{ "sp", 12}, /* ABI stack pointer */ \
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{ "sp", 12}, /* ABI stack pointer */ \
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{ "ln", 13}, /* arch link register */ \
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{ "ln", 13}, /* arch link register */ \
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{ "ptr", 14}, /* arch constant pointer */ \
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{ "ptr", 14}, /* arch constant pointer */ \
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{ "rc", 15}, /* arch constant register */ \
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{ "rc", 15}, /* arch constant register */ \
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{ "rz", 15}, /* arch zero */ \
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{ "rz", 15}, /* arch zero */ \
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}
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}
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/* Final prescan insn is called just before an instruction is
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/* Final prescan insn is called just before an instruction is
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output. In our case, we use this to detect the VLIW slot to which
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output. In our case, we use this to detect the VLIW slot to which
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the instruction has been assigned, preparatory to generating the
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the instruction has been assigned, preparatory to generating the
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VLIW output in ASM_OUTPUT_OPCODE. */
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VLIW output in ASM_OUTPUT_OPCODE. */
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#define FINAL_PRESCAN_INSN(insn, operand, nop) \
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#define FINAL_PRESCAN_INSN(insn, operand, nop) \
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picochip_final_prescan_insn (insn, operand,nop)
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picochip_final_prescan_insn (insn, operand,nop)
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|
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#define ASM_OUTPUT_OPCODE(FILE,PTR) \
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#define ASM_OUTPUT_OPCODE(FILE,PTR) \
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{ PTR = picochip_asm_output_opcode(FILE, PTR); }
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{ PTR = picochip_asm_output_opcode(FILE, PTR); }
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|
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#define PRINT_OPERAND(STREAM,X,CODE) \
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#define PRINT_OPERAND(STREAM,X,CODE) \
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picochip_print_operand(STREAM, X, CODE)
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picochip_print_operand(STREAM, X, CODE)
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|
|
#define PRINT_OPERAND_PUNCT_VALID_P(code) \
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#define PRINT_OPERAND_PUNCT_VALID_P(code) \
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(((code) == '|') || ((code) == '#') || ((code) == '>'))
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(((code) == '|') || ((code) == '#') || ((code) == '>'))
|
|
|
#define PRINT_OPERAND_ADDRESS(STREAM,X) \
|
#define PRINT_OPERAND_ADDRESS(STREAM,X) \
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picochip_print_operand_address(STREAM,X)
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picochip_print_operand_address(STREAM,X)
|
|
|
/* Output of Dispatch Tables */
|
/* Output of Dispatch Tables */
|
|
|
/* Initialise a data memory location to an absolute code label. Used
|
/* Initialise a data memory location to an absolute code label. Used
|
for building switch statement jump tables. Note - the format of the
|
for building switch statement jump tables. Note - the format of the
|
label must match that of the function picochip_output_label. */
|
label must match that of the function picochip_output_label. */
|
#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
|
#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
|
fprintf (stream, ".initWord _L%d\n", value);
|
fprintf (stream, ".initWord _L%d\n", value);
|
|
|
/* Assembler Commands for Alignment */
|
/* Assembler Commands for Alignment */
|
|
|
#define ASM_OUTPUT_SKIP(STREAM,BYTES) \
|
#define ASM_OUTPUT_SKIP(STREAM,BYTES) \
|
fprintf(STREAM, ".skip %u\n", BYTES);
|
fprintf(STREAM, ".skip %u\n", BYTES);
|
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
fprintf(STREAM, ".align %u\n", 1 << POWER);
|
fprintf(STREAM, ".align %u\n", 1 << POWER);
|
|
|
/* The elaborator doesn't output zero bytes in the text section. */
|
/* The elaborator doesn't output zero bytes in the text section. */
|
#define ASM_NO_SKIP_IN_TEXT 1
|
#define ASM_NO_SKIP_IN_TEXT 1
|
|
|
/* Controlling Debugging Information Format */
|
/* Controlling Debugging Information Format */
|
|
|
/* Macros Affecting All Debugging Formats */
|
/* Macros Affecting All Debugging Formats */
|
|
|
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
|
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
|
|
|
#define DWARF2_DEBUGGING_INFO
|
#define DWARF2_DEBUGGING_INFO
|
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
#define DWARF2_FRAME_INFO 1
|
#define DWARF2_FRAME_INFO 1
|
|
|
/* Generate .file/.loc directives, so that the assembler generates the
|
/* Generate .file/.loc directives, so that the assembler generates the
|
line table. */
|
line table. */
|
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
|
|
/* Miscellaneous Parameters */
|
/* Miscellaneous Parameters */
|
|
|
#define CASE_VECTOR_MODE HImode
|
#define CASE_VECTOR_MODE HImode
|
#define WORD_REGISTER_OPERATIONS
|
#define WORD_REGISTER_OPERATIONS
|
#define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
|
#define LOAD_EXTEND_OP(MODE) ((MODE) == QImode ? SIGN_EXTEND : ZERO_EXTEND)
|
#define MOVE_MAX 4
|
#define MOVE_MAX 4
|
#define SHIFT_COUNT_TRUNCATED 1
|
#define SHIFT_COUNT_TRUNCATED 1
|
#define Pmode HImode
|
#define Pmode HImode
|
#define FUNCTION_MODE QImode
|
#define FUNCTION_MODE QImode
|
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
|
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
|
|
|
#define ASM_LONG ":TODO:.word\t"
|
#define ASM_LONG ":TODO:.word\t"
|
|
|
/* Define builtins for selected special-purpose instructions. */
|
/* Define builtins for selected special-purpose instructions. */
|
enum picochip_builtins
|
enum picochip_builtins
|
{
|
{
|
PICOCHIP_BUILTIN_SBC,
|
PICOCHIP_BUILTIN_SBC,
|
PICOCHIP_BUILTIN_PUT,
|
PICOCHIP_BUILTIN_PUT,
|
PICOCHIP_BUILTIN_GET,
|
PICOCHIP_BUILTIN_GET,
|
PICOCHIP_BUILTIN_TESTPORT,
|
PICOCHIP_BUILTIN_TESTPORT,
|
PICOCHIP_BUILTIN_COPYSW,
|
PICOCHIP_BUILTIN_COPYSW,
|
PICOCHIP_BUILTIN_ADDS,
|
PICOCHIP_BUILTIN_ADDS,
|
PICOCHIP_BUILTIN_SUBS,
|
PICOCHIP_BUILTIN_SUBS,
|
PICOCHIP_BUILTIN_BREV,
|
PICOCHIP_BUILTIN_BREV,
|
PICOCHIP_BUILTIN_BYTESWAP,
|
PICOCHIP_BUILTIN_BYTESWAP,
|
PICOCHIP_BUILTIN_GET_ARRAY,
|
PICOCHIP_BUILTIN_GET_ARRAY,
|
PICOCHIP_BUILTIN_PUT_ARRAY,
|
PICOCHIP_BUILTIN_PUT_ARRAY,
|
PICOCHIP_BUILTIN_TESTPORT_ARRAY,
|
PICOCHIP_BUILTIN_TESTPORT_ARRAY,
|
PICOCHIP_BUILTIN_ASRI,
|
PICOCHIP_BUILTIN_ASRI,
|
PICOCHIP_BUILTIN_HALT
|
PICOCHIP_BUILTIN_HALT
|
};
|
};
|
|
|
#define NO_DOLLAR_IN_LABEL 1
|
#define NO_DOLLAR_IN_LABEL 1
|
#define NO_DOT_IN_LABEL 1
|
#define NO_DOT_IN_LABEL 1
|
|
|
/* The assembler does support LEB128, despite the auto-configure test
|
/* The assembler does support LEB128, despite the auto-configure test
|
not detecting this. */
|
not detecting this. */
|
#define HAVE_AS_LEB128 1
|
#define HAVE_AS_LEB128 1
|
|
|
/* The End */
|
/* The End */
|
|
|
