;; Scheduling description for PowerPC A2 processors.
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;; Scheduling description for PowerPC A2 processors.
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;; Contributed by Ben Elliston (bje@au.ibm.com)
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;; Contributed by Ben Elliston (bje@au.ibm.com)
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_automaton "ppca2")
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(define_automaton "ppca2")
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;; CPU units
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;; CPU units
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;; The multiplier pipeline.
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;; The multiplier pipeline.
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(define_cpu_unit "mult" "ppca2")
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(define_cpu_unit "mult" "ppca2")
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;; The auxillary processor unit (FP/vector unit).
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;; The auxillary processor unit (FP/vector unit).
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(define_cpu_unit "axu" "ppca2")
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(define_cpu_unit "axu" "ppca2")
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;; D.4.6
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;; D.4.6
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;; Some peculiarities for certain SPRs
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;; Some peculiarities for certain SPRs
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(define_insn_reservation "ppca2-mfcr" 1
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(define_insn_reservation "ppca2-mfcr" 1
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(and (eq_attr "type" "mfcr")
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"nothing")
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"nothing")
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(define_insn_reservation "ppca2-mfjmpr" 5
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(define_insn_reservation "ppca2-mfjmpr" 5
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(and (eq_attr "type" "mfjmpr")
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"nothing")
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"nothing")
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(define_insn_reservation "ppca2-mtjmpr" 5
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(define_insn_reservation "ppca2-mtjmpr" 5
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(and (eq_attr "type" "mtjmpr")
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"nothing")
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"nothing")
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;; D.4.8
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;; D.4.8
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(define_insn_reservation "ppca2-imul" 1
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(define_insn_reservation "ppca2-imul" 1
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"nothing")
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"nothing")
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;; FIXME: latency and multiplier reservation for 64-bit multiply?
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;; FIXME: latency and multiplier reservation for 64-bit multiply?
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(define_insn_reservation "ppca2-lmul" 6
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(define_insn_reservation "ppca2-lmul" 6
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(and (eq_attr "type" "lmul,lmul_compare")
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(and (eq_attr "type" "lmul,lmul_compare")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"mult*3")
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"mult*3")
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;; D.4.9
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;; D.4.9
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(define_insn_reservation "ppca2-idiv" 32
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(define_insn_reservation "ppca2-idiv" 32
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(and (eq_attr "type" "idiv")
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"mult*32")
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"mult*32")
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(define_insn_reservation "ppca2-ldiv" 65
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(define_insn_reservation "ppca2-ldiv" 65
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(and (eq_attr "type" "ldiv")
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"mult*65")
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"mult*65")
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;; D.4.13
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;; D.4.13
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(define_insn_reservation "ppca2-load" 5
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(define_insn_reservation "ppca2-load" 5
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"nothing")
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"nothing")
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;; D.8.1
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;; D.8.1
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(define_insn_reservation "ppca2-fp" 6
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(define_insn_reservation "ppca2-fp" 6
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(and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
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(and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only).
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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;; D.8.4
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;; D.8.4
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(define_insn_reservation "ppca2-fp-load" 6
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(define_insn_reservation "ppca2-fp-load" 6
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(and (eq_attr "type" "fpload,fpload_u,fpload_ux")
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(and (eq_attr "type" "fpload,fpload_u,fpload_ux")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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;; D.8.5
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;; D.8.5
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(define_insn_reservation "ppca2-fp-store" 2
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(define_insn_reservation "ppca2-fp-store" 2
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(and (eq_attr "type" "fpstore,fpstore_u,fpstore_ux")
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(and (eq_attr "type" "fpstore,fpstore_u,fpstore_ux")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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;; D.8.6
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;; D.8.6
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(define_insn_reservation "ppca2-fpcompare" 5
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(define_insn_reservation "ppca2-fpcompare" 5
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(and (eq_attr "type" "fpcompare")
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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;; D.8.7
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;; D.8.7
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;;
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;;
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;; Instructions from the same thread succeeding the floating-point
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;; Instructions from the same thread succeeding the floating-point
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;; divide cannot be executed until the floating-point divide has
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;; divide cannot be executed until the floating-point divide has
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;; completed. Since there is nothing else we can do, this thread will
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;; completed. Since there is nothing else we can do, this thread will
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;; just have to stall.
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;; just have to stall.
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(define_insn_reservation "ppca2-ddiv" 72
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(define_insn_reservation "ppca2-ddiv" 72
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(and (eq_attr "type" "ddiv")
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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(define_insn_reservation "ppca2-sdiv" 59
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(define_insn_reservation "ppca2-sdiv" 59
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(and (eq_attr "type" "sdiv")
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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;; D.8.8
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;; D.8.8
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;;
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;;
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;; Instructions from the same thread succeeding the floating-point
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;; Instructions from the same thread succeeding the floating-point
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;; divide cannot be executed until the floating-point divide has
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;; divide cannot be executed until the floating-point divide has
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;; completed. Since there is nothing else we can do, this thread will
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;; completed. Since there is nothing else we can do, this thread will
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;; just have to stall.
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;; just have to stall.
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(define_insn_reservation "ppca2-dsqrt" 69
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(define_insn_reservation "ppca2-dsqrt" 69
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(and (eq_attr "type" "dsqrt")
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(and (eq_attr "type" "dsqrt")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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(define_insn_reservation "ppca2-ssqrt" 65
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(define_insn_reservation "ppca2-ssqrt" 65
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(and (eq_attr "type" "ssqrt")
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(and (eq_attr "type" "ssqrt")
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(eq_attr "cpu" "ppca2"))
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(eq_attr "cpu" "ppca2"))
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"axu")
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"axu")
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