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[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [config/] [rs6000/] [e500mc.md] - Diff between revs 282 and 338

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;; Pipeline description for Motorola PowerPC e500mc core.
;; Pipeline description for Motorola PowerPC e500mc core.
;;   Copyright (C) 2008 Free Software Foundation, Inc.
;;   Copyright (C) 2008 Free Software Foundation, Inc.
;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;;
;; This file is part of GCC.
;; This file is part of GCC.
;;
;;
;; GCC is free software; you can redistribute it and/or modify it
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; option) any later version.
;;
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;; License for more details.
;;
;;
;; You should have received a copy of the GNU General Public License
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; along with GCC; see the file COPYING3.  If not see
;; .
;; .
;;
;;
;; e500mc 32-bit SU(2), LSU, FPU, BPU
;; e500mc 32-bit SU(2), LSU, FPU, BPU
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; Max issue 3 insns/clock cycle (includes 1 branch)
;; FP is half clocked, timings of other instructions are as in the e500v2.
;; FP is half clocked, timings of other instructions are as in the e500v2.
(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
(define_cpu_unit "e500mc_issue_0,e500mc_issue_1"   "e500mc_most")
(define_cpu_unit "e500mc_issue_0,e500mc_issue_1"   "e500mc_most")
(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
;; SU.
;; SU.
(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
;; MU.
;; MU.
(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
;; Non-pipelined division.
;; Non-pipelined division.
(define_cpu_unit "e500mc_mu_div" "e500mc_long")
(define_cpu_unit "e500mc_mu_div" "e500mc_long")
;; LSU.
;; LSU.
(define_cpu_unit "e500mc_lsu" "e500mc_most")
(define_cpu_unit "e500mc_lsu" "e500mc_most")
;; FPU.
;; FPU.
(define_cpu_unit "e500mc_fpu" "e500mc_most")
(define_cpu_unit "e500mc_fpu" "e500mc_most")
;; Branch unit.
;; Branch unit.
(define_cpu_unit "e500mc_bu" "e500mc_most")
(define_cpu_unit "e500mc_bu" "e500mc_most")
;; The following units are used to make the automata deterministic.
;; The following units are used to make the automata deterministic.
(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
;; The following sets to make automata deterministic when option ndfa is used.
;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
;; Some useful abbreviations.
;; Some useful abbreviations.
(define_reservation "e500mc_decode"
(define_reservation "e500mc_decode"
    "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
    "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
(define_reservation "e500mc_issue"
(define_reservation "e500mc_issue"
    "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
    "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
(define_reservation "e500mc_retire"
(define_reservation "e500mc_retire"
   "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
   "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
(define_reservation "e500mc_su_stage0"
(define_reservation "e500mc_su_stage0"
   "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
   "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
;; Simple SU insns.
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
(define_insn_reservation "e500mc_su" 1
  (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
  (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
                        delayed_compare,var_delayed_compare,fast_compare,\
                        delayed_compare,var_delayed_compare,fast_compare,\
                        shift,trap,var_shift_rotate,cntlz,exts,isel")
                        shift,trap,var_shift_rotate,cntlz,exts,isel")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_two" 1
(define_insn_reservation "e500mc_two" 1
  (and (eq_attr "type" "two")
  (and (eq_attr "type" "two")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
   e500mc_issue+e500mc_su_stage0+e500mc_retire")
   e500mc_issue+e500mc_su_stage0+e500mc_retire")
(define_insn_reservation "e500mc_three" 1
(define_insn_reservation "e500mc_three" 1
  (and (eq_attr "type" "three")
  (and (eq_attr "type" "three")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
   e500mc_issue+e500mc_su_stage0+e500mc_retire,\
   e500mc_issue+e500mc_su_stage0+e500mc_retire,\
   e500mc_issue+e500mc_su_stage0+e500mc_retire")
   e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Multiply.
;; Multiply.
(define_insn_reservation "e500mc_multiply" 4
(define_insn_reservation "e500mc_multiply" 4
  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
  "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
   e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
   e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
;; Divide. We use the average latency time here.
;; Divide. We use the average latency time here.
(define_insn_reservation "e500mc_divide" 14
(define_insn_reservation "e500mc_divide" 14
  (and (eq_attr "type" "idiv")
  (and (eq_attr "type" "idiv")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
  "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
   e500mc_mu_div*13")
   e500mc_mu_div*13")
;; Branch.
;; Branch.
(define_insn_reservation "e500mc_branch" 1
(define_insn_reservation "e500mc_branch" 1
  (and (eq_attr "type" "jmpreg,branch,isync")
  (and (eq_attr "type" "jmpreg,branch,isync")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_bu,e500mc_retire")
  "e500mc_decode,e500mc_bu,e500mc_retire")
;; CR logical.
;; CR logical.
(define_insn_reservation "e500mc_cr_logical" 1
(define_insn_reservation "e500mc_cr_logical" 1
  (and (eq_attr "type" "cr_logical,delayed_cr")
  (and (eq_attr "type" "cr_logical,delayed_cr")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_bu,e500mc_retire")
  "e500mc_decode,e500mc_bu,e500mc_retire")
;; Mfcr.
;; Mfcr.
(define_insn_reservation "e500mc_mfcr" 1
(define_insn_reservation "e500mc_mfcr" 1
  (and (eq_attr "type" "mfcr")
  (and (eq_attr "type" "mfcr")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtcrf.
;; Mtcrf.
(define_insn_reservation "e500mc_mtcrf" 1
(define_insn_reservation "e500mc_mtcrf" 1
  (and (eq_attr "type" "mtcr")
  (and (eq_attr "type" "mtcr")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
;; Mtjmpr.
;; Mtjmpr.
(define_insn_reservation "e500mc_mtjmpr" 1
(define_insn_reservation "e500mc_mtjmpr" 1
  (and (eq_attr "type" "mtjmpr,mfjmpr")
  (and (eq_attr "type" "mtjmpr,mfjmpr")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Brinc.
;; Brinc.
(define_insn_reservation "e500mc_brinc" 1
(define_insn_reservation "e500mc_brinc" 1
  (and (eq_attr "type" "brinc")
  (and (eq_attr "type" "brinc")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Loads.
;; Loads.
(define_insn_reservation "e500mc_load" 3
(define_insn_reservation "e500mc_load" 3
  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
                        load_l,sync")
                        load_l,sync")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpload" 4
(define_insn_reservation "e500mc_fpload" 4
  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
;; Stores.
;; Stores.
(define_insn_reservation "e500mc_store" 3
(define_insn_reservation "e500mc_store" 3
  (and (eq_attr "type" "store,store_ux,store_u,store_c")
  (and (eq_attr "type" "store,store_ux,store_u,store_c")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
(define_insn_reservation "e500mc_fpstore" 3
(define_insn_reservation "e500mc_fpstore" 3
  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
  "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
;; The following ignores the retire unit to avoid a large automata.
;; The following ignores the retire unit to avoid a large automata.
;; Simple FP.
;; Simple FP.
(define_insn_reservation "e500mc_simple_float" 8
(define_insn_reservation "e500mc_simple_float" 8
  (and (eq_attr "type" "fpsimple")
  (and (eq_attr "type" "fpsimple")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu")
  "e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
;; FP.
;; FP.
(define_insn_reservation "e500mc_float" 8
(define_insn_reservation "e500mc_float" 8
  (and (eq_attr "type" "fp")
  (and (eq_attr "type" "fp")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu")
  "e500mc_decode,e500mc_issue+e500mc_fpu")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
(define_insn_reservation "e500mc_fpcompare" 8
(define_insn_reservation "e500mc_fpcompare" 8
  (and (eq_attr "type" "fpcompare")
  (and (eq_attr "type" "fpcompare")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu")
  "e500mc_decode,e500mc_issue+e500mc_fpu")
(define_insn_reservation "e500mc_dmul" 10
(define_insn_reservation "e500mc_dmul" 10
  (and (eq_attr "type" "dmul")
  (and (eq_attr "type" "dmul")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu")
  "e500mc_decode,e500mc_issue+e500mc_fpu")
;; FP divides are not pipelined.
;; FP divides are not pipelined.
(define_insn_reservation "e500mc_sdiv" 36
(define_insn_reservation "e500mc_sdiv" 36
  (and (eq_attr "type" "sdiv")
  (and (eq_attr "type" "sdiv")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
  "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
(define_insn_reservation "e500mc_ddiv" 66
(define_insn_reservation "e500mc_ddiv" 66
  (and (eq_attr "type" "ddiv")
  (and (eq_attr "type" "ddiv")
       (eq_attr "cpu" "ppce500mc"))
       (eq_attr "cpu" "ppce500mc"))
  "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
  "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
 
 

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