;; Expander definitions for vector support between altivec & vsx. No
|
;; Expander definitions for vector support between altivec & vsx. No
|
;; instructions are in this file, this file provides the generic vector
|
;; instructions are in this file, this file provides the generic vector
|
;; expander, and the actual vector instructions will be in altivec.md and
|
;; expander, and the actual vector instructions will be in altivec.md and
|
;; vsx.md
|
;; vsx.md
|
|
|
;; Copyright (C) 2009, 2010
|
;; Copyright (C) 2009, 2010
|
;; Free Software Foundation, Inc.
|
;; Free Software Foundation, Inc.
|
;; Contributed by Michael Meissner
|
;; Contributed by Michael Meissner
|
|
|
;; This file is part of GCC.
|
;; This file is part of GCC.
|
|
|
;; GCC is free software; you can redistribute it and/or modify it
|
;; GCC is free software; you can redistribute it and/or modify it
|
;; under the terms of the GNU General Public License as published
|
;; under the terms of the GNU General Public License as published
|
;; by the Free Software Foundation; either version 3, or (at your
|
;; by the Free Software Foundation; either version 3, or (at your
|
;; option) any later version.
|
;; option) any later version.
|
|
|
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
;; License for more details.
|
;; License for more details.
|
|
|
;; You should have received a copy of the GNU General Public License
|
;; You should have received a copy of the GNU General Public License
|
;; along with GCC; see the file COPYING3. If not see
|
;; along with GCC; see the file COPYING3. If not see
|
;; .
|
;; .
|
|
|
|
|
;; Vector int modes
|
;; Vector int modes
|
(define_mode_iterator VEC_I [V16QI V8HI V4SI])
|
(define_mode_iterator VEC_I [V16QI V8HI V4SI])
|
|
|
;; Vector float modes
|
;; Vector float modes
|
(define_mode_iterator VEC_F [V4SF V2DF])
|
(define_mode_iterator VEC_F [V4SF V2DF])
|
|
|
;; Vector arithmetic modes
|
;; Vector arithmetic modes
|
(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
|
(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF])
|
|
|
;; Vector modes that need alginment via permutes
|
;; Vector modes that need alginment via permutes
|
(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
|
(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
|
|
|
;; Vector logical modes
|
;; Vector logical modes
|
(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
|
(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI])
|
|
|
;; Vector modes for moves. Don't do TImode here.
|
;; Vector modes for moves. Don't do TImode here.
|
(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
|
(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF])
|
|
|
;; Vector modes for types that don't need a realignment under VSX
|
;; Vector modes for types that don't need a realignment under VSX
|
(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
|
(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF])
|
|
|
;; Vector comparison modes
|
;; Vector comparison modes
|
(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
|
(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF])
|
|
|
;; Vector init/extract modes
|
;; Vector init/extract modes
|
(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
|
(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
|
|
|
;; Vector modes for 64-bit base types
|
;; Vector modes for 64-bit base types
|
(define_mode_iterator VEC_64 [V2DI V2DF])
|
(define_mode_iterator VEC_64 [V2DI V2DF])
|
|
|
;; Vector reload iterator
|
;; Vector reload iterator
|
(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
|
(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
|
|
|
;; Base type from vector mode
|
;; Base type from vector mode
|
(define_mode_attr VEC_base [(V16QI "QI")
|
(define_mode_attr VEC_base [(V16QI "QI")
|
(V8HI "HI")
|
(V8HI "HI")
|
(V4SI "SI")
|
(V4SI "SI")
|
(V2DI "DI")
|
(V2DI "DI")
|
(V4SF "SF")
|
(V4SF "SF")
|
(V2DF "DF")
|
(V2DF "DF")
|
(TI "TI")])
|
(TI "TI")])
|
|
|
;; Same size integer type for floating point data
|
;; Same size integer type for floating point data
|
(define_mode_attr VEC_int [(V4SF "v4si")
|
(define_mode_attr VEC_int [(V4SF "v4si")
|
(V2DF "v2di")])
|
(V2DF "v2di")])
|
|
|
(define_mode_attr VEC_INT [(V4SF "V4SI")
|
(define_mode_attr VEC_INT [(V4SF "V4SI")
|
(V2DF "V2DI")])
|
(V2DF "V2DI")])
|
|
|
;; constants for unspec
|
;; constants for unspec
|
(define_constants
|
(define_constants
|
[(UNSPEC_PREDICATE 400)])
|
[(UNSPEC_PREDICATE 400)])
|
|
|
|
|
;; Vector move instructions.
|
;; Vector move instructions.
|
(define_expand "mov"
|
(define_expand "mov"
|
[(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
|
[(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
|
(match_operand:VEC_M 1 "any_operand" ""))]
|
(match_operand:VEC_M 1 "any_operand" ""))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
{
|
{
|
if (can_create_pseudo_p ())
|
if (can_create_pseudo_p ())
|
{
|
{
|
if (CONSTANT_P (operands[1])
|
if (CONSTANT_P (operands[1])
|
&& !easy_vector_constant (operands[1], mode))
|
&& !easy_vector_constant (operands[1], mode))
|
operands[1] = force_const_mem (mode, operands[1]);
|
operands[1] = force_const_mem (mode, operands[1]);
|
|
|
else if (!vlogical_operand (operands[0], mode)
|
else if (!vlogical_operand (operands[0], mode)
|
&& !vlogical_operand (operands[1], mode))
|
&& !vlogical_operand (operands[1], mode))
|
operands[1] = force_reg (mode, operands[1]);
|
operands[1] = force_reg (mode, operands[1]);
|
}
|
}
|
})
|
})
|
|
|
;; Generic vector floating point load/store instructions. These will match
|
;; Generic vector floating point load/store instructions. These will match
|
;; insns defined in vsx.md or altivec.md depending on the switches.
|
;; insns defined in vsx.md or altivec.md depending on the switches.
|
(define_expand "vector_load_"
|
(define_expand "vector_load_"
|
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
|
(match_operand:VEC_M 1 "memory_operand" ""))]
|
(match_operand:VEC_M 1 "memory_operand" ""))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_store_"
|
(define_expand "vector_store_"
|
[(set (match_operand:VEC_M 0 "memory_operand" "")
|
[(set (match_operand:VEC_M 0 "memory_operand" "")
|
(match_operand:VEC_M 1 "vfloat_operand" ""))]
|
(match_operand:VEC_M 1 "vfloat_operand" ""))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
;; Splits if a GPR register was chosen for the move
|
;; Splits if a GPR register was chosen for the move
|
(define_split
|
(define_split
|
[(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
|
[(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
|
(match_operand:VEC_L 1 "input_operand" ""))]
|
(match_operand:VEC_L 1 "input_operand" ""))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|
&& reload_completed
|
&& reload_completed
|
&& gpr_or_gpr_p (operands[0], operands[1])"
|
&& gpr_or_gpr_p (operands[0], operands[1])"
|
[(pc)]
|
[(pc)]
|
{
|
{
|
rs6000_split_multireg_move (operands[0], operands[1]);
|
rs6000_split_multireg_move (operands[0], operands[1]);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
|
|
;; Reload patterns for vector operations. We may need an addtional base
|
;; Reload patterns for vector operations. We may need an addtional base
|
;; register to convert the reg+offset addressing to reg+reg for vector
|
;; register to convert the reg+offset addressing to reg+reg for vector
|
;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
|
;; registers and reg+reg or (reg+reg)&(-16) addressing to just an index
|
;; register for gpr registers.
|
;; register for gpr registers.
|
(define_expand "reload___store"
|
(define_expand "reload___store"
|
[(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
|
[(parallel [(match_operand:VEC_R 0 "memory_operand" "m")
|
(match_operand:VEC_R 1 "gpc_reg_operand" "r")
|
(match_operand:VEC_R 1 "gpc_reg_operand" "r")
|
(match_operand:P 2 "register_operand" "=&b")])]
|
(match_operand:P 2 "register_operand" "=&b")])]
|
""
|
""
|
{
|
{
|
rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
|
rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "reload___load"
|
(define_expand "reload___load"
|
[(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
|
[(parallel [(match_operand:VEC_R 0 "gpc_reg_operand" "=&r")
|
(match_operand:VEC_R 1 "memory_operand" "m")
|
(match_operand:VEC_R 1 "memory_operand" "m")
|
(match_operand:P 2 "register_operand" "=&b")])]
|
(match_operand:P 2 "register_operand" "=&b")])]
|
""
|
""
|
{
|
{
|
rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
|
rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;; Reload sometimes tries to move the address to a GPR, and can generate
|
;; Reload sometimes tries to move the address to a GPR, and can generate
|
;; invalid RTL for addresses involving AND -16. Allow addresses involving
|
;; invalid RTL for addresses involving AND -16. Allow addresses involving
|
;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
|
;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
|
|
|
(define_insn_and_split "*vec_reload_and_plus_"
|
(define_insn_and_split "*vec_reload_and_plus_"
|
[(set (match_operand:P 0 "gpc_reg_operand" "=b")
|
[(set (match_operand:P 0 "gpc_reg_operand" "=b")
|
(and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
|
(and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
|
(match_operand:P 2 "reg_or_cint_operand" "rI"))
|
(match_operand:P 2 "reg_or_cint_operand" "rI"))
|
(const_int -16)))]
|
(const_int -16)))]
|
"(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
|
"(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
|
"#"
|
"#"
|
"&& reload_completed"
|
"&& reload_completed"
|
[(set (match_dup 0)
|
[(set (match_dup 0)
|
(plus:P (match_dup 1)
|
(plus:P (match_dup 1)
|
(match_dup 2)))
|
(match_dup 2)))
|
(parallel [(set (match_dup 0)
|
(parallel [(set (match_dup 0)
|
(and:P (match_dup 0)
|
(and:P (match_dup 0)
|
(const_int -16)))
|
(const_int -16)))
|
(clobber:CC (scratch:CC))])])
|
(clobber:CC (scratch:CC))])])
|
|
|
;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
|
;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
|
;; address to a register because there is no clobber of a (scratch), so we add
|
;; address to a register because there is no clobber of a (scratch), so we add
|
;; it here.
|
;; it here.
|
(define_insn_and_split "*vec_reload_and_reg_"
|
(define_insn_and_split "*vec_reload_and_reg_"
|
[(set (match_operand:P 0 "gpc_reg_operand" "=b")
|
[(set (match_operand:P 0 "gpc_reg_operand" "=b")
|
(and:P (match_operand:P 1 "gpc_reg_operand" "r")
|
(and:P (match_operand:P 1 "gpc_reg_operand" "r")
|
(const_int -16)))]
|
(const_int -16)))]
|
"(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
|
"(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
|
"#"
|
"#"
|
"&& reload_completed"
|
"&& reload_completed"
|
[(parallel [(set (match_dup 0)
|
[(parallel [(set (match_dup 0)
|
(and:P (match_dup 1)
|
(and:P (match_dup 1)
|
(const_int -16)))
|
(const_int -16)))
|
(clobber:CC (scratch:CC))])])
|
(clobber:CC (scratch:CC))])])
|
|
|
;; Generic floating point vector arithmetic support
|
;; Generic floating point vector arithmetic support
|
(define_expand "add3"
|
(define_expand "add3"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "sub3"
|
(define_expand "sub3"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "mul3"
|
(define_expand "mul3"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
"(VECTOR_UNIT_VSX_P (mode)
|
"(VECTOR_UNIT_VSX_P (mode)
|
|| (VECTOR_UNIT_ALTIVEC_P (mode) && TARGET_FUSED_MADD))"
|
|| (VECTOR_UNIT_ALTIVEC_P (mode) && TARGET_FUSED_MADD))"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "div3"
|
(define_expand "div3"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
"VECTOR_UNIT_VSX_P (mode)"
|
"VECTOR_UNIT_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "neg2"
|
(define_expand "neg2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
|
emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "abs2"
|
(define_expand "abs2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
|
emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "smin3"
|
(define_expand "smin3"
|
[(set (match_operand:VEC_F 0 "register_operand" "")
|
[(set (match_operand:VEC_F 0 "register_operand" "")
|
(smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
|
(smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
|
(match_operand:VEC_F 2 "register_operand" "")))]
|
(match_operand:VEC_F 2 "register_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "smax3"
|
(define_expand "smax3"
|
[(set (match_operand:VEC_F 0 "register_operand" "")
|
[(set (match_operand:VEC_F 0 "register_operand" "")
|
(smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
|
(smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
|
(match_operand:VEC_F 2 "register_operand" "")))]
|
(match_operand:VEC_F 2 "register_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
|
|
(define_expand "sqrt2"
|
(define_expand "sqrt2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_VSX_P (mode)"
|
"VECTOR_UNIT_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "ftrunc2"
|
(define_expand "ftrunc2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_ceil2"
|
(define_expand "vector_ceil2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
|
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
|
UNSPEC_FRIP))]
|
UNSPEC_FRIP))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_floor2"
|
(define_expand "vector_floor2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
|
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
|
UNSPEC_FRIM))]
|
UNSPEC_FRIM))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_btrunc2"
|
(define_expand "vector_btrunc2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_copysign3"
|
(define_expand "vector_copysign3"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(if_then_else:VEC_F
|
(if_then_else:VEC_F
|
(ge:VEC_F (match_operand:VEC_F 2 "vfloat_operand" "")
|
(ge:VEC_F (match_operand:VEC_F 2 "vfloat_operand" "")
|
(match_dup 3))
|
(match_dup 3))
|
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" ""))
|
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" ""))
|
(neg:VEC_F (abs:VEC_F (match_dup 1)))))]
|
(neg:VEC_F (abs:VEC_F (match_dup 1)))))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
|
emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
|
operands[2]));
|
operands[2]));
|
DONE;
|
DONE;
|
}
|
}
|
|
|
operands[3] = CONST0_RTX (mode);
|
operands[3] = CONST0_RTX (mode);
|
}")
|
}")
|
|
|
|
|
;; Vector comparisons
|
;; Vector comparisons
|
(define_expand "vcond"
|
(define_expand "vcond"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(if_then_else:VEC_F
|
(if_then_else:VEC_F
|
(match_operator 3 "comparison_operator"
|
(match_operator 3 "comparison_operator"
|
[(match_operand:VEC_F 4 "vfloat_operand" "")
|
[(match_operand:VEC_F 4 "vfloat_operand" "")
|
(match_operand:VEC_F 5 "vfloat_operand" "")])
|
(match_operand:VEC_F 5 "vfloat_operand" "")])
|
(match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
(match_operand:VEC_F 2 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}")
|
}")
|
|
|
(define_expand "vcond"
|
(define_expand "vcond"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(if_then_else:VEC_I
|
(if_then_else:VEC_I
|
(match_operator 3 "comparison_operator"
|
(match_operator 3 "comparison_operator"
|
[(match_operand:VEC_I 4 "vint_operand" "")
|
[(match_operand:VEC_I 4 "vint_operand" "")
|
(match_operand:VEC_I 5 "vint_operand" "")])
|
(match_operand:VEC_I 5 "vint_operand" "")])
|
(match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}")
|
}")
|
|
|
(define_expand "vcondu"
|
(define_expand "vcondu"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(if_then_else:VEC_I
|
(if_then_else:VEC_I
|
(match_operator 3 "comparison_operator"
|
(match_operator 3 "comparison_operator"
|
[(match_operand:VEC_I 4 "vint_operand" "")
|
[(match_operand:VEC_I 4 "vint_operand" "")
|
(match_operand:VEC_I 5 "vint_operand" "")])
|
(match_operand:VEC_I 5 "vint_operand" "")])
|
(match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"
|
"
|
{
|
{
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
|
operands[3], operands[4], operands[5]))
|
operands[3], operands[4], operands[5]))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
}")
|
}")
|
|
|
(define_expand "vector_eq"
|
(define_expand "vector_eq"
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
(eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_gt"
|
(define_expand "vector_gt"
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
(gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_ge"
|
(define_expand "vector_ge"
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
|
(ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(ge:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
(match_operand:VEC_C 2 "vlogical_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_gtu"
|
(define_expand "vector_gtu"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_geu"
|
(define_expand "vector_geu"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_P (mode)"
|
"")
|
"")
|
|
|
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
|
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
|
;; which is in the reverse order that we want
|
;; which is in the reverse order that we want
|
(define_expand "vector_select_"
|
(define_expand "vector_select_"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(if_then_else:VEC_L
|
(if_then_else:VEC_L
|
(ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
|
(ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
|
(const_int 0))
|
(const_int 0))
|
(match_operand:VEC_L 2 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_select__uns"
|
(define_expand "vector_select__uns"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(if_then_else:VEC_L
|
(if_then_else:VEC_L
|
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
|
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
|
(const_int 0))
|
(const_int 0))
|
(match_operand:VEC_L 2 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
;; Expansions that compare vectors producing a vector result and a predicate,
|
;; Expansions that compare vectors producing a vector result and a predicate,
|
;; setting CR6 to indicate a combined status
|
;; setting CR6 to indicate a combined status
|
(define_expand "vector_eq__p"
|
(define_expand "vector_eq__p"
|
[(parallel
|
[(parallel
|
[(set (reg:CC 74)
|
[(set (reg:CC 74)
|
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
|
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
|
(match_operand:VEC_A 2 "vlogical_operand" ""))]
|
(match_operand:VEC_A 2 "vlogical_operand" ""))]
|
UNSPEC_PREDICATE))
|
UNSPEC_PREDICATE))
|
(set (match_operand:VEC_A 0 "vlogical_operand" "")
|
(set (match_operand:VEC_A 0 "vlogical_operand" "")
|
(eq:VEC_A (match_dup 1)
|
(eq:VEC_A (match_dup 1)
|
(match_dup 2)))])]
|
(match_dup 2)))])]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_gt__p"
|
(define_expand "vector_gt__p"
|
[(parallel
|
[(parallel
|
[(set (reg:CC 74)
|
[(set (reg:CC 74)
|
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
|
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
|
(match_operand:VEC_A 2 "vlogical_operand" ""))]
|
(match_operand:VEC_A 2 "vlogical_operand" ""))]
|
UNSPEC_PREDICATE))
|
UNSPEC_PREDICATE))
|
(set (match_operand:VEC_A 0 "vlogical_operand" "")
|
(set (match_operand:VEC_A 0 "vlogical_operand" "")
|
(gt:VEC_A (match_dup 1)
|
(gt:VEC_A (match_dup 1)
|
(match_dup 2)))])]
|
(match_dup 2)))])]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_ge__p"
|
(define_expand "vector_ge__p"
|
[(parallel
|
[(parallel
|
[(set (reg:CC 74)
|
[(set (reg:CC 74)
|
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
|
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
|
(match_operand:VEC_F 2 "vfloat_operand" ""))]
|
(match_operand:VEC_F 2 "vfloat_operand" ""))]
|
UNSPEC_PREDICATE))
|
UNSPEC_PREDICATE))
|
(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(ge:VEC_F (match_dup 1)
|
(ge:VEC_F (match_dup 1)
|
(match_dup 2)))])]
|
(match_dup 2)))])]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vector_gtu__p"
|
(define_expand "vector_gtu__p"
|
[(parallel
|
[(parallel
|
[(set (reg:CC 74)
|
[(set (reg:CC 74)
|
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
|
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" ""))]
|
(match_operand:VEC_I 2 "vint_operand" ""))]
|
UNSPEC_PREDICATE))
|
UNSPEC_PREDICATE))
|
(set (match_operand:VEC_I 0 "vlogical_operand" "")
|
(set (match_operand:VEC_I 0 "vlogical_operand" "")
|
(gtu:VEC_I (match_dup 1)
|
(gtu:VEC_I (match_dup 1)
|
(match_dup 2)))])]
|
(match_dup 2)))])]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
;; AltiVec/VSX predicates.
|
;; AltiVec/VSX predicates.
|
|
|
(define_expand "cr6_test_for_zero"
|
(define_expand "cr6_test_for_zero"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(eq:SI (reg:CC 74)
|
(eq:SI (reg:CC 74)
|
(const_int 0)))]
|
(const_int 0)))]
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_zero_reverse"
|
(define_expand "cr6_test_for_zero_reverse"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(eq:SI (reg:CC 74)
|
(eq:SI (reg:CC 74)
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_lt"
|
(define_expand "cr6_test_for_lt"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lt:SI (reg:CC 74)
|
(lt:SI (reg:CC 74)
|
(const_int 0)))]
|
(const_int 0)))]
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"")
|
"")
|
|
|
(define_expand "cr6_test_for_lt_reverse"
|
(define_expand "cr6_test_for_lt_reverse"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lt:SI (reg:CC 74)
|
(lt:SI (reg:CC 74)
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
(set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"TARGET_ALTIVEC || TARGET_VSX"
|
"")
|
"")
|
|
|
|
|
;; Vector logical instructions
|
;; Vector logical instructions
|
(define_expand "xor3"
|
(define_expand "xor3"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "ior3"
|
(define_expand "ior3"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "and3"
|
(define_expand "and3"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
(match_operand:VEC_L 2 "vlogical_operand" "")))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "one_cmpl2"
|
(define_expand "one_cmpl2"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
|
(not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "nor3"
|
(define_expand "nor3"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 2 "vlogical_operand" ""))))]
|
(match_operand:VEC_L 2 "vlogical_operand" ""))))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "andc3"
|
(define_expand "andc3"
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
|
(and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
|
(and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" ""))
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
(match_operand:VEC_L 1 "vlogical_operand" "")))]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"")
|
"")
|
|
|
;; Same size conversions
|
;; Same size conversions
|
(define_expand "float2"
|
(define_expand "float2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(float:VEC_F (match_operand: 1 "vint_operand" "")))]
|
(float:VEC_F (match_operand: 1 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
|
emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "unsigned_float2"
|
(define_expand "unsigned_float2"
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
|
(unsigned_float:VEC_F (match_operand: 1 "vint_operand" "")))]
|
(unsigned_float:VEC_F (match_operand: 1 "vint_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
|
emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "fix_trunc2"
|
(define_expand "fix_trunc2"
|
[(set (match_operand: 0 "vint_operand" "")
|
[(set (match_operand: 0 "vint_operand" "")
|
(fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
|
emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "fixuns_trunc2"
|
(define_expand "fixuns_trunc2"
|
[(set (match_operand: 0 "vint_operand" "")
|
[(set (match_operand: 0 "vint_operand" "")
|
(unsigned_fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
(unsigned_fix: (match_operand:VEC_F 1 "vfloat_operand" "")))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)"
|
"
|
"
|
{
|
{
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode))
|
{
|
{
|
emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
|
emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
|
|
;; Vector initialization, set, extract
|
;; Vector initialization, set, extract
|
(define_expand "vec_init"
|
(define_expand "vec_init"
|
[(match_operand:VEC_E 0 "vlogical_operand" "")
|
[(match_operand:VEC_E 0 "vlogical_operand" "")
|
(match_operand:VEC_E 1 "" "")]
|
(match_operand:VEC_E 1 "" "")]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
{
|
{
|
rs6000_expand_vector_init (operands[0], operands[1]);
|
rs6000_expand_vector_init (operands[0], operands[1]);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_set"
|
(define_expand "vec_set"
|
[(match_operand:VEC_E 0 "vlogical_operand" "")
|
[(match_operand:VEC_E 0 "vlogical_operand" "")
|
(match_operand: 1 "register_operand" "")
|
(match_operand: 1 "register_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
{
|
{
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_extract"
|
(define_expand "vec_extract"
|
[(match_operand: 0 "register_operand" "")
|
[(match_operand: 0 "register_operand" "")
|
(match_operand:VEC_E 1 "vlogical_operand" "")
|
(match_operand:VEC_E 1 "vlogical_operand" "")
|
(match_operand 2 "const_int_operand" "")]
|
(match_operand 2 "const_int_operand" "")]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
{
|
{
|
rs6000_expand_vector_extract (operands[0], operands[1],
|
rs6000_expand_vector_extract (operands[0], operands[1],
|
INTVAL (operands[2]));
|
INTVAL (operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;; Interleave patterns
|
;; Interleave patterns
|
(define_expand "vec_interleave_highv4sf"
|
(define_expand "vec_interleave_highv4sf"
|
[(set (match_operand:V4SF 0 "vfloat_operand" "")
|
[(set (match_operand:V4SF 0 "vfloat_operand" "")
|
(vec_merge:V4SF
|
(vec_merge:V4SF
|
(vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
|
(vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 2)
|
(const_int 2)
|
(const_int 1)
|
(const_int 1)
|
(const_int 3)]))
|
(const_int 3)]))
|
(vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
|
(vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
|
(parallel [(const_int 2)
|
(parallel [(const_int 2)
|
(const_int 0)
|
(const_int 0)
|
(const_int 3)
|
(const_int 3)
|
(const_int 1)]))
|
(const_int 1)]))
|
(const_int 5)))]
|
(const_int 5)))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"")
|
"")
|
|
|
(define_expand "vec_interleave_lowv4sf"
|
(define_expand "vec_interleave_lowv4sf"
|
[(set (match_operand:V4SF 0 "vfloat_operand" "")
|
[(set (match_operand:V4SF 0 "vfloat_operand" "")
|
(vec_merge:V4SF
|
(vec_merge:V4SF
|
(vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
|
(vec_select:V4SF (match_operand:V4SF 1 "vfloat_operand" "")
|
(parallel [(const_int 2)
|
(parallel [(const_int 2)
|
(const_int 0)
|
(const_int 0)
|
(const_int 3)
|
(const_int 3)
|
(const_int 1)]))
|
(const_int 1)]))
|
(vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
|
(vec_select:V4SF (match_operand:V4SF 2 "vfloat_operand" "")
|
(parallel [(const_int 0)
|
(parallel [(const_int 0)
|
(const_int 2)
|
(const_int 2)
|
(const_int 1)
|
(const_int 1)
|
(const_int 3)]))
|
(const_int 3)]))
|
(const_int 5)))]
|
(const_int 5)))]
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"")
|
"")
|
|
|
(define_expand "vec_interleave_high"
|
(define_expand "vec_interleave_high"
|
[(set (match_operand:VEC_64 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_64 0 "vfloat_operand" "")
|
(vec_concat:VEC_64
|
(vec_concat:VEC_64
|
(vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
|
(vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
|
(parallel [(const_int 0)]))
|
(parallel [(const_int 0)]))
|
(vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
|
(vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
|
(parallel [(const_int 0)]))))]
|
(parallel [(const_int 0)]))))]
|
"VECTOR_UNIT_VSX_P (mode)"
|
"VECTOR_UNIT_VSX_P (mode)"
|
"")
|
"")
|
|
|
(define_expand "vec_interleave_low"
|
(define_expand "vec_interleave_low"
|
[(set (match_operand:VEC_64 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_64 0 "vfloat_operand" "")
|
(vec_concat:VEC_64
|
(vec_concat:VEC_64
|
(vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
|
(vec_select: (match_operand:VEC_64 1 "vfloat_operand" "")
|
(parallel [(const_int 1)]))
|
(parallel [(const_int 1)]))
|
(vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
|
(vec_select: (match_operand:VEC_64 2 "vfloat_operand" "")
|
(parallel [(const_int 1)]))))]
|
(parallel [(const_int 1)]))))]
|
"VECTOR_UNIT_VSX_P (mode)"
|
"VECTOR_UNIT_VSX_P (mode)"
|
"")
|
"")
|
|
|
|
|
;; Convert double word types to single word types
|
;; Convert double word types to single word types
|
(define_expand "vec_pack_trunc_v2df"
|
(define_expand "vec_pack_trunc_v2df"
|
[(match_operand:V4SF 0 "vfloat_operand" "")
|
[(match_operand:V4SF 0 "vfloat_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
{
|
{
|
rtx r1 = gen_reg_rtx (V4SFmode);
|
rtx r1 = gen_reg_rtx (V4SFmode);
|
rtx r2 = gen_reg_rtx (V4SFmode);
|
rtx r2 = gen_reg_rtx (V4SFmode);
|
|
|
emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
|
emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
|
emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2));
|
emit_insn (gen_vec_extract_evenv4sf (operands[0], r1, r2));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_pack_sfix_trunc_v2df"
|
(define_expand "vec_pack_sfix_trunc_v2df"
|
[(match_operand:V4SI 0 "vint_operand" "")
|
[(match_operand:V4SI 0 "vint_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
{
|
{
|
rtx r1 = gen_reg_rtx (V4SImode);
|
rtx r1 = gen_reg_rtx (V4SImode);
|
rtx r2 = gen_reg_rtx (V4SImode);
|
rtx r2 = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
|
emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
|
emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
|
emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_pack_ufix_trunc_v2df"
|
(define_expand "vec_pack_ufix_trunc_v2df"
|
[(match_operand:V4SI 0 "vint_operand" "")
|
[(match_operand:V4SI 0 "vint_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 1 "vfloat_operand" "")
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
(match_operand:V2DF 2 "vfloat_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
|
{
|
{
|
rtx r1 = gen_reg_rtx (V4SImode);
|
rtx r1 = gen_reg_rtx (V4SImode);
|
rtx r2 = gen_reg_rtx (V4SImode);
|
rtx r2 = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
|
emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
|
emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
|
emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
|
emit_insn (gen_vec_extract_evenv4si (operands[0], r1, r2));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;; Convert single word types to double word
|
;; Convert single word types to double word
|
(define_expand "vec_unpacks_hi_v4sf"
|
(define_expand "vec_unpacks_hi_v4sf"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SF 1 "vfloat_operand" "")]
|
(match_operand:V4SF 1 "vfloat_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SFmode);
|
rtx reg = gen_reg_rtx (V4SFmode);
|
|
|
emit_insn (gen_vec_interleave_highv4sf (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_highv4sf (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_unpacks_lo_v4sf"
|
(define_expand "vec_unpacks_lo_v4sf"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SF 1 "vfloat_operand" "")]
|
(match_operand:V4SF 1 "vfloat_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SFmode);
|
rtx reg = gen_reg_rtx (V4SFmode);
|
|
|
emit_insn (gen_vec_interleave_lowv4sf (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_lowv4sf (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_unpacks_float_hi_v4si"
|
(define_expand "vec_unpacks_float_hi_v4si"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SI 1 "vint_operand" "")]
|
(match_operand:V4SI 1 "vint_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SImode);
|
rtx reg = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_unpacks_float_lo_v4si"
|
(define_expand "vec_unpacks_float_lo_v4si"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SI 1 "vint_operand" "")]
|
(match_operand:V4SI 1 "vint_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SImode);
|
rtx reg = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_unpacku_float_hi_v4si"
|
(define_expand "vec_unpacku_float_hi_v4si"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SI 1 "vint_operand" "")]
|
(match_operand:V4SI 1 "vint_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SImode);
|
rtx reg = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_highv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "vec_unpacku_float_lo_v4si"
|
(define_expand "vec_unpacku_float_lo_v4si"
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
[(match_operand:V2DF 0 "vfloat_operand" "")
|
(match_operand:V4SI 1 "vint_operand" "")]
|
(match_operand:V4SI 1 "vint_operand" "")]
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
|
{
|
{
|
rtx reg = gen_reg_rtx (V4SImode);
|
rtx reg = gen_reg_rtx (V4SImode);
|
|
|
emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vec_interleave_lowv4si (reg, operands[1], operands[1]));
|
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
|
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
|
|
;; Align vector loads with a permute.
|
;; Align vector loads with a permute.
|
(define_expand "vec_realign_load_"
|
(define_expand "vec_realign_load_"
|
[(match_operand:VEC_K 0 "vlogical_operand" "")
|
[(match_operand:VEC_K 0 "vlogical_operand" "")
|
(match_operand:VEC_K 1 "vlogical_operand" "")
|
(match_operand:VEC_K 1 "vlogical_operand" "")
|
(match_operand:VEC_K 2 "vlogical_operand" "")
|
(match_operand:VEC_K 2 "vlogical_operand" "")
|
(match_operand:V16QI 3 "vlogical_operand" "")]
|
(match_operand:V16QI 3 "vlogical_operand" "")]
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
"VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)"
|
{
|
{
|
emit_insn (gen_altivec_vperm_ (operands[0], operands[1], operands[2],
|
emit_insn (gen_altivec_vperm_ (operands[0], operands[1], operands[2],
|
operands[3]));
|
operands[3]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
|
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
|
;; since the load already handles it.
|
;; since the load already handles it.
|
(define_expand "movmisalign"
|
(define_expand "movmisalign"
|
[(set (match_operand:VEC_N 0 "vfloat_operand" "")
|
[(set (match_operand:VEC_N 0 "vfloat_operand" "")
|
(match_operand:VEC_N 1 "vfloat_operand" ""))]
|
(match_operand:VEC_N 1 "vfloat_operand" ""))]
|
"VECTOR_MEM_VSX_P (mode) && TARGET_ALLOW_MOVMISALIGN"
|
"VECTOR_MEM_VSX_P (mode) && TARGET_ALLOW_MOVMISALIGN"
|
"")
|
"")
|
|
|
|
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; Vector shift left in bits. Currently supported ony for shift
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; General shift amounts can be supported using vslo + vsl. We're
|
;; General shift amounts can be supported using vslo + vsl. We're
|
;; not expecting to see these yet (the vectorizer currently
|
;; not expecting to see these yet (the vectorizer currently
|
;; generates only shifts divisible by byte_size).
|
;; generates only shifts divisible by byte_size).
|
(define_expand "vec_shl_"
|
(define_expand "vec_shl_"
|
[(match_operand:VEC_L 0 "vlogical_operand" "")
|
[(match_operand:VEC_L 0 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx bitshift = operands[2];
|
rtx bitshift = operands[2];
|
rtx shift;
|
rtx shift;
|
rtx insn;
|
rtx insn;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT byteshift_val;
|
HOST_WIDE_INT byteshift_val;
|
|
|
if (! CONSTANT_P (bitshift))
|
if (! CONSTANT_P (bitshift))
|
FAIL;
|
FAIL;
|
bitshift_val = INTVAL (bitshift);
|
bitshift_val = INTVAL (bitshift);
|
if (bitshift_val & 0x7)
|
if (bitshift_val & 0x7)
|
FAIL;
|
FAIL;
|
byteshift_val = bitshift_val >> 3;
|
byteshift_val = bitshift_val >> 3;
|
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
|
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
|
{
|
{
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
|
insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
|
insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
|
shift);
|
shift);
|
}
|
}
|
else
|
else
|
{
|
{
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
shift);
|
shift);
|
}
|
}
|
|
|
emit_insn (insn);
|
emit_insn (insn);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; Vector shift right in bits. Currently supported ony for shift
|
;; Vector shift right in bits. Currently supported ony for shift
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; amounts that can be expressed as byte shifts (divisible by 8).
|
;; General shift amounts can be supported using vsro + vsr. We're
|
;; General shift amounts can be supported using vsro + vsr. We're
|
;; not expecting to see these yet (the vectorizer currently
|
;; not expecting to see these yet (the vectorizer currently
|
;; generates only shifts divisible by byte_size).
|
;; generates only shifts divisible by byte_size).
|
(define_expand "vec_shr_"
|
(define_expand "vec_shr_"
|
[(match_operand:VEC_L 0 "vlogical_operand" "")
|
[(match_operand:VEC_L 0 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:VEC_L 1 "vlogical_operand" "")
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
(match_operand:QI 2 "reg_or_short_operand" "")]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"
|
"
|
{
|
{
|
rtx bitshift = operands[2];
|
rtx bitshift = operands[2];
|
rtx shift;
|
rtx shift;
|
rtx insn;
|
rtx insn;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT bitshift_val;
|
HOST_WIDE_INT byteshift_val;
|
HOST_WIDE_INT byteshift_val;
|
|
|
if (! CONSTANT_P (bitshift))
|
if (! CONSTANT_P (bitshift))
|
FAIL;
|
FAIL;
|
bitshift_val = INTVAL (bitshift);
|
bitshift_val = INTVAL (bitshift);
|
if (bitshift_val & 0x7)
|
if (bitshift_val & 0x7)
|
FAIL;
|
FAIL;
|
byteshift_val = 16 - (bitshift_val >> 3);
|
byteshift_val = 16 - (bitshift_val >> 3);
|
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
|
if (TARGET_VSX && (byteshift_val & 0x3) == 0)
|
{
|
{
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
|
insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
|
insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1],
|
shift);
|
shift);
|
}
|
}
|
else
|
else
|
{
|
{
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
shift = gen_rtx_CONST_INT (QImode, byteshift_val);
|
insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1],
|
shift);
|
shift);
|
}
|
}
|
|
|
emit_insn (insn);
|
emit_insn (insn);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; Expanders for rotate each element in a vector
|
;; Expanders for rotate each element in a vector
|
(define_expand "vrotl3"
|
(define_expand "vrotl3"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
;; Expanders for arithmetic shift left on each vector element
|
;; Expanders for arithmetic shift left on each vector element
|
(define_expand "vashl3"
|
(define_expand "vashl3"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
;; Expanders for logical shift right on each vector element
|
;; Expanders for logical shift right on each vector element
|
(define_expand "vlshr3"
|
(define_expand "vlshr3"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
;; Expanders for arithmetic shift right on each vector element
|
;; Expanders for arithmetic shift right on each vector element
|
(define_expand "vashr3"
|
(define_expand "vashr3"
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
[(set (match_operand:VEC_I 0 "vint_operand" "")
|
(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
(match_operand:VEC_I 2 "vint_operand" "")))]
|
"TARGET_ALTIVEC"
|
"TARGET_ALTIVEC"
|
"")
|
"")
|
|
|
;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
|
;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
|
|
|
(define_expand "absv2sf2"
|
(define_expand "absv2sf2"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
|
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"")
|
"")
|
|
|
(define_expand "negv2sf2"
|
(define_expand "negv2sf2"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
|
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"")
|
"")
|
|
|
(define_expand "addv2sf3"
|
(define_expand "addv2sf3"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"
|
"
|
{
|
{
|
if (TARGET_SPE)
|
if (TARGET_SPE)
|
{
|
{
|
/* We need to make a note that we clobber SPEFSCR. */
|
/* We need to make a note that we clobber SPEFSCR. */
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
|
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
|
gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
emit_insn (par);
|
emit_insn (par);
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "subv2sf3"
|
(define_expand "subv2sf3"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"
|
"
|
{
|
{
|
if (TARGET_SPE)
|
if (TARGET_SPE)
|
{
|
{
|
/* We need to make a note that we clobber SPEFSCR. */
|
/* We need to make a note that we clobber SPEFSCR. */
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
|
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
|
gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
emit_insn (par);
|
emit_insn (par);
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "mulv2sf3"
|
(define_expand "mulv2sf3"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"
|
"
|
{
|
{
|
if (TARGET_SPE)
|
if (TARGET_SPE)
|
{
|
{
|
/* We need to make a note that we clobber SPEFSCR. */
|
/* We need to make a note that we clobber SPEFSCR. */
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
|
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
|
gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
emit_insn (par);
|
emit_insn (par);
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
(define_expand "divv2sf3"
|
(define_expand "divv2sf3"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
|
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"TARGET_PAIRED_FLOAT || TARGET_SPE"
|
"
|
"
|
{
|
{
|
if (TARGET_SPE)
|
if (TARGET_SPE)
|
{
|
{
|
/* We need to make a note that we clobber SPEFSCR. */
|
/* We need to make a note that we clobber SPEFSCR. */
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
|
|
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
|
gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
|
gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
|
emit_insn (par);
|
emit_insn (par);
|
DONE;
|
DONE;
|
}
|
}
|
}")
|
}")
|
|
|
