; Options for the SH port of the compiler.
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; Options for the SH port of the compiler.
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; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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;
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;
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; This file is part of GCC.
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; This file is part of GCC.
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;
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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; version.
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;
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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; for more details.
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;
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;
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; You should have received a copy of the GNU General Public License
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; along with GCC; see the file COPYING3. If not see
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; .
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; .
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;; Used for various architecture options.
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;; Used for various architecture options.
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Mask(SH_E)
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Mask(SH_E)
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;; Set if the default precision of th FPU is single.
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;; Set if the default precision of th FPU is single.
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Mask(FPU_SINGLE)
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Mask(FPU_SINGLE)
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;; Set if we should generate code using type 2A insns.
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;; Set if we should generate code using type 2A insns.
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Mask(HARD_SH2A)
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Mask(HARD_SH2A)
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;; Set if we should generate code using type 2A DF insns.
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;; Set if we should generate code using type 2A DF insns.
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Mask(HARD_SH2A_DOUBLE)
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Mask(HARD_SH2A_DOUBLE)
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;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
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;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
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Mask(HARD_SH4)
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Mask(HARD_SH4)
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;; Set if we should generate code for a SH5 CPU (either ISA).
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;; Set if we should generate code for a SH5 CPU (either ISA).
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Mask(SH5)
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Mask(SH5)
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;; Set if we should save all target registers.
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;; Set if we should save all target registers.
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Mask(SAVE_ALL_TARGET_REGS)
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Mask(SAVE_ALL_TARGET_REGS)
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m1
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m1
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Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
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Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
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Generate SH1 code
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Generate SH1 code
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m2
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m2
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Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
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Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
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Generate SH2 code
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Generate SH2 code
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m2a
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m2a
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Target RejectNegative Condition(SUPPORT_SH2A)
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Target RejectNegative Condition(SUPPORT_SH2A)
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Generate default double-precision SH2a-FPU code
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Generate default double-precision SH2a-FPU code
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m2a-nofpu
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m2a-nofpu
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Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
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Generate SH2a FPU-less code
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Generate SH2a FPU-less code
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m2a-single
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m2a-single
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Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
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Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
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Generate default single-precision SH2a-FPU code
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Generate default single-precision SH2a-FPU code
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m2a-single-only
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m2a-single-only
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Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
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Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
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Generate only single-precision SH2a-FPU code
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Generate only single-precision SH2a-FPU code
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m2e
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m2e
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Target RejectNegative Condition(SUPPORT_SH2E)
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Target RejectNegative Condition(SUPPORT_SH2E)
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Generate SH2e code
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Generate SH2e code
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m3
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m3
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Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
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Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
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Generate SH3 code
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Generate SH3 code
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m3e
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m3e
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Target RejectNegative Condition(SUPPORT_SH3E)
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Target RejectNegative Condition(SUPPORT_SH3E)
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Generate SH3e code
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Generate SH3e code
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m4
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m4
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Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
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Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
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Generate SH4 code
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Generate SH4 code
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m4-100
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m4-100
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Target RejectNegative Condition(SUPPORT_SH4)
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Target RejectNegative Condition(SUPPORT_SH4)
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Generate SH4-100 code
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Generate SH4-100 code
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m4-200
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m4-200
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Target RejectNegative Condition(SUPPORT_SH4)
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Target RejectNegative Condition(SUPPORT_SH4)
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Generate SH4-200 code
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Generate SH4-200 code
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;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
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;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
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;; pipeline - irrespective of ABI.
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;; pipeline - irrespective of ABI.
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m4-300
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m4-300
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Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
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Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
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Generate SH4-300 code
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Generate SH4-300 code
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m4-nofpu
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m4-nofpu
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Generate SH4 FPU-less code
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Generate SH4 FPU-less code
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m4-100-nofpu
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m4-100-nofpu
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Generate SH4-100 FPU-less code
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Generate SH4-100 FPU-less code
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m4-200-nofpu
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m4-200-nofpu
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Generate SH4-200 FPU-less code
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Generate SH4-200 FPU-less code
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m4-300-nofpu
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m4-300-nofpu
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
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Generate SH4-300 FPU-less code
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Generate SH4-300 FPU-less code
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m4-340
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m4-340
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
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Generate code for SH4 340 series (MMU/FPU-less)
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Generate code for SH4 340 series (MMU/FPU-less)
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;; passes -isa=sh4-nommu-nofpu to the assembler.
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;; passes -isa=sh4-nommu-nofpu to the assembler.
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m4-400
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m4-400
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Generate code for SH4 400 series (MMU/FPU-less)
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Generate code for SH4 400 series (MMU/FPU-less)
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;; passes -isa=sh4-nommu-nofpu to the assembler.
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;; passes -isa=sh4-nommu-nofpu to the assembler.
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m4-500
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m4-500
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
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Generate code for SH4 500 series (FPU-less).
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Generate code for SH4 500 series (FPU-less).
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;; passes -isa=sh4-nofpu to the assembler.
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;; passes -isa=sh4-nofpu to the assembler.
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m4-single
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m4-single
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Generate default single-precision SH4 code
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Generate default single-precision SH4 code
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m4-100-single
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m4-100-single
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Generate default single-precision SH4-100 code
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Generate default single-precision SH4-100 code
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m4-200-single
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m4-200-single
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
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Generate default single-precision SH4-200 code
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Generate default single-precision SH4-200 code
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m4-300-single
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m4-300-single
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
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Generate default single-precision SH4-300 code
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Generate default single-precision SH4-300 code
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m4-single-only
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m4-single-only
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Generate only single-precision SH4 code
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Generate only single-precision SH4 code
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m4-100-single-only
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m4-100-single-only
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Generate only single-precision SH4-100 code
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Generate only single-precision SH4-100 code
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m4-200-single-only
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m4-200-single-only
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
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Generate only single-precision SH4-200 code
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Generate only single-precision SH4-200 code
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m4-300-single-only
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m4-300-single-only
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
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Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
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Generate only single-precision SH4-300 code
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Generate only single-precision SH4-300 code
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m4a
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m4a
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Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
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Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
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Generate SH4a code
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Generate SH4a code
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m4a-nofpu
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m4a-nofpu
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Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
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Generate SH4a FPU-less code
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Generate SH4a FPU-less code
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m4a-single
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m4a-single
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Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
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Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
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Generate default single-precision SH4a code
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Generate default single-precision SH4a code
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m4a-single-only
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m4a-single-only
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Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
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Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
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Generate only single-precision SH4a code
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Generate only single-precision SH4a code
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m4al
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m4al
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Target RejectNegative Condition(SUPPORT_SH4AL)
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Target RejectNegative Condition(SUPPORT_SH4AL)
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Generate SH4al-dsp code
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Generate SH4al-dsp code
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m5-32media
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m5-32media
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
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Generate 32-bit SHmedia code
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Generate 32-bit SHmedia code
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m5-32media-nofpu
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m5-32media-nofpu
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
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Generate 32-bit FPU-less SHmedia code
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Generate 32-bit FPU-less SHmedia code
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m5-64media
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m5-64media
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Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
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Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
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Generate 64-bit SHmedia code
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Generate 64-bit SHmedia code
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m5-64media-nofpu
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m5-64media-nofpu
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Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
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Generate 64-bit FPU-less SHmedia code
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Generate 64-bit FPU-less SHmedia code
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m5-compact
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m5-compact
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
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Generate SHcompact code
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Generate SHcompact code
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m5-compact-nofpu
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m5-compact-nofpu
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
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Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
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Generate FPU-less SHcompact code
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Generate FPU-less SHcompact code
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madjust-unroll
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madjust-unroll
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Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
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Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
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Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
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Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
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mb
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mb
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Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
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Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
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Generate code in big endian mode
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Generate code in big endian mode
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mbigtable
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mbigtable
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Target Report RejectNegative Mask(BIGTABLE)
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Target Report RejectNegative Mask(BIGTABLE)
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Generate 32-bit offsets in switch tables
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Generate 32-bit offsets in switch tables
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mbitops
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mbitops
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Target Report RejectNegative Mask(BITOPS)
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Target Report RejectNegative Mask(BITOPS)
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Generate bit instructions
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Generate bit instructions
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mbranch-cost=
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mbranch-cost=
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Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
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Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
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Cost to assume for a branch insn
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Cost to assume for a branch insn
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mcbranchdi
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mcbranchdi
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Target Var(TARGET_CBRANCHDI4)
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Target Var(TARGET_CBRANCHDI4)
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Enable cbranchdi4 pattern
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Enable cbranchdi4 pattern
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mcmpeqdi
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mcmpeqdi
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Target Var(TARGET_CMPEQDI_T)
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Target Var(TARGET_CMPEQDI_T)
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Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
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Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
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mcut2-workaround
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mcut2-workaround
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Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
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Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
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Enable SH5 cut2 workaround
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Enable SH5 cut2 workaround
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mdalign
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mdalign
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Target Report RejectNegative Mask(ALIGN_DOUBLE)
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Target Report RejectNegative Mask(ALIGN_DOUBLE)
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Align doubles at 64-bit boundaries
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Align doubles at 64-bit boundaries
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mdiv=
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mdiv=
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Target RejectNegative Joined Var(sh_div_str) Init("")
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Target RejectNegative Joined Var(sh_div_str) Init("")
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Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
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Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
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mdivsi3_libfunc=
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mdivsi3_libfunc=
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Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
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Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
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Specify name for 32 bit signed division function
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Specify name for 32 bit signed division function
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mfmovd
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mfmovd
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Target RejectNegative Mask(FMOVD)
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Target RejectNegative Mask(FMOVD)
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Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
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Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
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mfixed-range=
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mfixed-range=
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Target RejectNegative Joined Var(sh_fixed_range_str)
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Target RejectNegative Joined Var(sh_fixed_range_str)
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Specify range of registers to make fixed
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Specify range of registers to make fixed
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|
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mfused-madd
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mfused-madd
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Target Var(TARGET_FMAC)
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Target Var(TARGET_FMAC)
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Enable the use of the fused floating point multiply-accumulate operation
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Enable the use of the fused floating point multiply-accumulate operation
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mgettrcost=
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mgettrcost=
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Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
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Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
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Cost to assume for gettr insn
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Cost to assume for gettr insn
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|
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mhitachi
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mhitachi
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Target Report RejectNegative Mask(HITACHI)
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Target Report RejectNegative Mask(HITACHI)
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Follow Renesas (formerly Hitachi) / SuperH calling conventions
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Follow Renesas (formerly Hitachi) / SuperH calling conventions
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|
|
mieee
|
mieee
|
Target Report Mask(IEEE)
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Target Report Mask(IEEE)
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Increase the IEEE compliance for floating-point code
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Increase the IEEE compliance for floating-point code
|
|
|
mindexed-addressing
|
mindexed-addressing
|
Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
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Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
|
Enable the use of the indexed addressing mode for SHmedia32/SHcompact
|
Enable the use of the indexed addressing mode for SHmedia32/SHcompact
|
|
|
minline-ic_invalidate
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minline-ic_invalidate
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Target Report Var(TARGET_INLINE_IC_INVALIDATE)
|
Target Report Var(TARGET_INLINE_IC_INVALIDATE)
|
inline code to invalidate instruction cache entries after setting up nested function trampolines
|
inline code to invalidate instruction cache entries after setting up nested function trampolines
|
|
|
minvalid-symbols
|
minvalid-symbols
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Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
|
Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
|
Assume symbols might be invalid
|
Assume symbols might be invalid
|
|
|
misize
|
misize
|
Target Report RejectNegative Mask(DUMPISIZE)
|
Target Report RejectNegative Mask(DUMPISIZE)
|
Annotate assembler instructions with estimated addresses
|
Annotate assembler instructions with estimated addresses
|
|
|
ml
|
ml
|
Target Report RejectNegative Mask(LITTLE_ENDIAN)
|
Target Report RejectNegative Mask(LITTLE_ENDIAN)
|
Generate code in little endian mode
|
Generate code in little endian mode
|
|
|
mnomacsave
|
mnomacsave
|
Target Report RejectNegative Mask(NOMACSAVE)
|
Target Report RejectNegative Mask(NOMACSAVE)
|
Mark MAC register as call-clobbered
|
Mark MAC register as call-clobbered
|
|
|
;; ??? This option is not useful, but is retained in case there are people
|
;; ??? This option is not useful, but is retained in case there are people
|
;; who are still relying on it. It may be deleted in the future.
|
;; who are still relying on it. It may be deleted in the future.
|
mpadstruct
|
mpadstruct
|
Target Report RejectNegative Mask(PADSTRUCT)
|
Target Report RejectNegative Mask(PADSTRUCT)
|
Make structs a multiple of 4 bytes (warning: ABI altered)
|
Make structs a multiple of 4 bytes (warning: ABI altered)
|
|
|
mprefergot
|
mprefergot
|
Target Report RejectNegative Mask(PREFERGOT)
|
Target Report RejectNegative Mask(PREFERGOT)
|
Emit function-calls using global offset table when generating PIC
|
Emit function-calls using global offset table when generating PIC
|
|
|
mpt-fixed
|
mpt-fixed
|
Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
|
Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
|
Assume pt* instructions won't trap
|
Assume pt* instructions won't trap
|
|
|
mrelax
|
mrelax
|
Target Report RejectNegative Mask(RELAX)
|
Target Report RejectNegative Mask(RELAX)
|
Shorten address references during linking
|
Shorten address references during linking
|
|
|
mrenesas
|
mrenesas
|
Target Mask(HITACHI) MaskExists
|
Target Mask(HITACHI) MaskExists
|
Follow Renesas (formerly Hitachi) / SuperH calling conventions
|
Follow Renesas (formerly Hitachi) / SuperH calling conventions
|
|
|
mspace
|
mspace
|
Target Report RejectNegative Mask(SMALLCODE)
|
Target Report RejectNegative Mask(SMALLCODE)
|
Deprecated. Use -Os instead
|
Deprecated. Use -Os instead
|
|
|
multcost=
|
multcost=
|
Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
|
Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
|
Cost to assume for a multiply insn
|
Cost to assume for a multiply insn
|
|
|
musermode
|
musermode
|
Target Report RejectNegative Mask(USERMODE)
|
Target Report RejectNegative Mask(USERMODE)
|
Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
|
Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
|
|
|
;; We might want to enable this by default for TARGET_HARD_SH4, because
|
;; We might want to enable this by default for TARGET_HARD_SH4, because
|
;; zero-offset branches have zero latency. Needs some benchmarking.
|
;; zero-offset branches have zero latency. Needs some benchmarking.
|
mpretend-cmove
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mpretend-cmove
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Target Var(TARGET_PRETEND_CMOVE)
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Target Var(TARGET_PRETEND_CMOVE)
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Pretend a branch-around-a-move is a conditional move.
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Pretend a branch-around-a-move is a conditional move.
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