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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 298 |
Rev 338 |
/* Make sure that the H8 backend does not generate a div
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/* Make sure that the H8 backend does not generate a div
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instruction in a delay slot. */
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instruction in a delay slot. */
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/* { dg-options "-Os" } */
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/* { dg-options "-Os" } */
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/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
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/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
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/* { dg-final { scan-assembler-not "\tbra/s\t.*\n\tdiv*" } } */
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/* { dg-final { scan-assembler-not "\tbra/s\t.*\n\tdiv*" } } */
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extern volatile unsigned long timer_ticks;
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extern volatile unsigned long timer_ticks;
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#define timer_ms_elapsed(ticks) (((unsigned long)(timer_ticks-ticks))/10)
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#define timer_ms_elapsed(ticks) (((unsigned long)(timer_ticks-ticks))/10)
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unsigned long ticks;
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unsigned long ticks;
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unsigned tst_read( unsigned char idx )
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unsigned tst_read( unsigned char idx )
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{
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{
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switch( idx )
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switch( idx )
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{
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{
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case 0x62: return timer_ms_elapsed(ticks);
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case 0x62: return timer_ms_elapsed(ticks);
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case 0x61: return timer_ticks;
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case 0x61: return timer_ticks;
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default: return 0;
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default: return 0;
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}
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}
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}
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}
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