URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.dg/] [tree-ssa/] [pr23848-4.c] - Diff between revs 298 and 338

Rev 298	Rev 338
`/* PR middle-end/23848 */`	`/* PR middle-end/23848 */`
`/* { dg-do compile } */`	`/* { dg-do compile } */`
`/* { dg-options "-O2 -fdump-tree-optimized" } */`	`/* { dg-options "-O2 -fdump-tree-optimized" } */`

`void bar (char , char , char , char , int);`	`void bar (char , char , char , char , int);`
`void foo (int size)`	`void foo (int size)`
`{`	`{`
`char temp[size];`	`char temp[size];`
`temp[size-1] = '\0';`	`temp[size-1] = '\0';`
`{`	`{`
`char temp2[size];`	`char temp2[size];`
`{`	`{`
`char temp3[size];`	`char temp3[size];`
`{`	`{`
`char temp4[size];`	`char temp4[size];`
`bar (temp, temp2, temp3, temp4, size);`	`bar (temp, temp2, temp3, temp4, size);`
`}`	`}`
`}`	`}`
`__asm __volatile ("" : : "r" (&temp[0]), "r" (&temp2[0]) : "memory");`	`__asm __volatile ("" : : "r" (&temp[0]), "r" (&temp2[0]) : "memory");`
`}`	`}`
`}`	`}`

`/* { dg-final { scan-tree-dump-times "__builtin_stack_save" 1 "optimized"} } */`	`/* { dg-final { scan-tree-dump-times "__builtin_stack_save" 1 "optimized"} } */`
`/* { dg-final { scan-tree-dump-times "__builtin_stack_restore" 1 "optimized"} } */`	`/* { dg-final { scan-tree-dump-times "__builtin_stack_restore" 1 "optimized"} } */`
`/* { dg-final { cleanup-tree-dump "optimized" } } */`	`/* { dg-final { cleanup-tree-dump "optimized" } } */`