URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vmlsQ_laneu32.c] - Diff between revs 313 and 338

Rev 313	Rev 338
/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */	/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */
`/* This file was autogenerated by neon-testgen. */`	`/* This file was autogenerated by neon-testgen. */`

`/* { dg-do assemble } */`	`/* { dg-do assemble } */`
`/* { dg-require-effective-target arm_neon_ok } */`	`/* { dg-require-effective-target arm_neon_ok } */`
`/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */`	`/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */`

`#include "arm_neon.h"`	`#include "arm_neon.h"`

`void test_vmlsQ_laneu32 (void)`	`void test_vmlsQ_laneu32 (void)`
`{`	`{`
`uint32x4_t out_uint32x4_t;`	`uint32x4_t out_uint32x4_t;`
`uint32x4_t arg0_uint32x4_t;`	`uint32x4_t arg0_uint32x4_t;`
`uint32x4_t arg1_uint32x4_t;`	`uint32x4_t arg1_uint32x4_t;`
`uint32x2_t arg2_uint32x2_t;`	`uint32x2_t arg2_uint32x2_t;`

`out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);`	`out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);`
`}`	`}`

`/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */`	`/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */`
`/* { dg-final { cleanup-saved-temps } } */`	`/* { dg-final { cleanup-saved-temps } } */`