URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse-1.c] - Diff between revs 318 and 338

Rev 318	Rev 338
`/* PR 12902 */`	`/* PR 12902 */`
`/* { dg-do compile } */`	`/* { dg-do compile } */`
`/* { dg-options "-O1 -msse" } */`	`/* { dg-options "-O1 -msse" } */`
`/* { dg-require-effective-target sse } */`	`/* { dg-require-effective-target sse } */`

`#include <xmmintrin.h>`	`#include <xmmintrin.h>`

`typedef union`	`typedef union`
`{`	`{`
`int i[4];`	`int i[4];`
`float f[4];`	`float f[4];`
`__m128 v;`	`__m128 v;`
`} vector4_t;`	`} vector4_t;`

`void`	`void`
`swizzle (const void a, vector4_t b, vector4_t * c)`	`swizzle (const void a, vector4_t b, vector4_t * c)`
`{`	`{`
`b->v = _mm_loadl_pi (b->v, (__m64 *) a);`	`b->v = _mm_loadl_pi (b->v, (__m64 *) a);`
`c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);`	`c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);`
`}`	`}`

`/* While one legal rendering of each statement would be movaps;movlps;movaps,`	`/* While one legal rendering of each statement would be movaps;movlps;movaps,`
`we can implmenent this with just movlps;movlps. Since we do now, anything`	`we can implmenent this with just movlps;movlps. Since we do now, anything`
`less would be a regression. */`	`less would be a regression. */`
`/* { dg-final { scan-assembler-not "movaps" } } */`	`/* { dg-final { scan-assembler-not "movaps" } } */`
`/* { dg-final { scan-assembler "movlps" } } */`	`/* { dg-final { scan-assembler "movlps" } } */`