URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 318 |
Rev 338 |
/* { dg-do run } */
|
/* { dg-do run } */
|
/* { dg-options "-O2 -msse2" } */
|
/* { dg-options "-O2 -msse2" } */
|
/* { dg-require-effective-target sse2 } */
|
/* { dg-require-effective-target sse2 } */
|
|
|
#ifndef CHECK_H
|
#ifndef CHECK_H
|
#define CHECK_H "sse2-check.h"
|
#define CHECK_H "sse2-check.h"
|
#endif
|
#endif
|
|
|
#ifndef TEST
|
#ifndef TEST
|
#define TEST sse2_test
|
#define TEST sse2_test
|
#endif
|
#endif
|
|
|
#define N 0xb
|
#define N 0xb
|
|
|
#include CHECK_H
|
#include CHECK_H
|
|
|
#include <emmintrin.h>
|
#include <emmintrin.h>
|
|
|
static __m128i
|
static __m128i
|
__attribute__((noinline, unused))
|
__attribute__((noinline, unused))
|
test (__m128i s1)
|
test (__m128i s1)
|
{
|
{
|
return _mm_srli_epi16 (s1, N);
|
return _mm_srli_epi16 (s1, N);
|
}
|
}
|
|
|
static void
|
static void
|
TEST (void)
|
TEST (void)
|
{
|
{
|
union128i_w u, s;
|
union128i_w u, s;
|
short e[8] = {0};
|
short e[8] = {0};
|
unsigned short tmp;
|
unsigned short tmp;
|
int i;
|
int i;
|
|
|
s.x = _mm_set_epi16 (1, -2, 3, -4, 5, 6, 0x7000, 0x9000);
|
s.x = _mm_set_epi16 (1, -2, 3, -4, 5, 6, 0x7000, 0x9000);
|
|
|
u.x = test (s.x);
|
u.x = test (s.x);
|
|
|
if (N < 16)
|
if (N < 16)
|
for (i = 0; i < 8; i++)
|
for (i = 0; i < 8; i++)
|
{
|
{
|
tmp = s.a[i];
|
tmp = s.a[i];
|
e[i] = tmp >> N;
|
e[i] = tmp >> N;
|
}
|
}
|
|
|
if (check_union128i_w (u, e))
|
if (check_union128i_w (u, e))
|
abort ();
|
abort ();
|
}
|
}
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.