URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [branch-1.c] - Diff between revs 321 and 338

Rev 321	Rev 338
`/* Octeon targets should use "bbit" instructions for these "if" statements,`	`/* Octeon targets should use "bbit" instructions for these "if" statements,`
`but we test for "bbit" elsewhere. On other targets, we should implement`	`but we test for "bbit" elsewhere. On other targets, we should implement`
`the "if" statements using an "andi" instruction followed by a branch`	`the "if" statements using an "andi" instruction followed by a branch`
`on zero. */`	`on zero. */`
`/* { dg-options "-O2 forbid_cpu=octeon" } */`	`/* { dg-options "-O2 forbid_cpu=octeon" } */`

`void bar (void);`	`void bar (void);`
`NOMIPS16 void f1 (int x) { if (x & 4) bar (); }`	`NOMIPS16 void f1 (int x) { if (x & 4) bar (); }`
`NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); }`	`NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); }`
`NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); }`	`NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); }`
`NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }`	`NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }`
`/* { dg-final { scan-assembler "\tandi\t.\tandi\t.\tandi\t.\tandi\t" } } /`	`/* { dg-final { scan-assembler "\tandi\t.\tandi\t.\tandi\t.\tandi\t" } } /`
`/* { dg-final { scan-assembler-not "\tsrl\t" } } */`	`/* { dg-final { scan-assembler-not "\tsrl\t" } } */`
`/* { dg-final { scan-assembler-not "\tsra\t" } } */`	`/* { dg-final { scan-assembler-not "\tsra\t" } } */`