/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
|
/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
|
/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
|
/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
|
/* { dg-require-effective-target powerpc_altivec_ok } */
|
/* { dg-require-effective-target powerpc_altivec_ok } */
|
/* { dg-options "-maltivec -mabi=altivec -O2" } */
|
/* { dg-options "-maltivec -mabi=altivec -O2" } */
|
|
|
/* Check that "easy" AltiVec constants are correctly synthesized. */
|
/* Check that "easy" AltiVec constants are correctly synthesized. */
|
|
|
extern void abort (void);
|
extern void abort (void);
|
|
|
typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
|
typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
|
typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
|
typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
|
typedef __attribute__ ((vector_size (16))) unsigned int v4si;
|
typedef __attribute__ ((vector_size (16))) unsigned int v4si;
|
|
|
char w[16] __attribute__((aligned(16)));
|
char w[16] __attribute__((aligned(16)));
|
|
|
|
|
/* Emulate the vspltis? instructions on a 16-byte array of chars. */
|
/* Emulate the vspltis? instructions on a 16-byte array of chars. */
|
|
|
void vspltisb (char *v, int val)
|
void vspltisb (char *v, int val)
|
{
|
{
|
int i;
|
int i;
|
for (i = 0; i < 16; i++)
|
for (i = 0; i < 16; i++)
|
v[i] = val;
|
v[i] = val;
|
}
|
}
|
|
|
void vspltish (char *v, int val)
|
void vspltish (char *v, int val)
|
{
|
{
|
int i;
|
int i;
|
for (i = 0; i < 16; i += 2)
|
for (i = 0; i < 16; i += 2)
|
v[i] = val >> 7, v[i + 1] = val;
|
v[i] = val >> 7, v[i + 1] = val;
|
}
|
}
|
|
|
void vspltisw (char *v, int val)
|
void vspltisw (char *v, int val)
|
{
|
{
|
int i;
|
int i;
|
for (i = 0; i < 16; i += 4)
|
for (i = 0; i < 16; i += 4)
|
v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
|
v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
|
}
|
}
|
|
|
|
|
/* Use three different check functions for each mode-instruction pair.
|
/* Use three different check functions for each mode-instruction pair.
|
The callers have no typecasting and no addressable vectors, to make
|
The callers have no typecasting and no addressable vectors, to make
|
the test more robust. */
|
the test more robust. */
|
|
|
void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
|
void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
|
{
|
{
|
if (memcmp (&v1, v2, 16))
|
if (memcmp (&v1, v2, 16))
|
abort ();
|
abort ();
|
}
|
}
|
|
|
void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
|
void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
|
{
|
{
|
if (memcmp (&v1, v2, 16))
|
if (memcmp (&v1, v2, 16))
|
abort ();
|
abort ();
|
}
|
}
|
|
|
void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
|
void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
|
{
|
{
|
if (memcmp (&v1, v2, 16))
|
if (memcmp (&v1, v2, 16))
|
abort ();
|
abort ();
|
}
|
}
|
|
|
|
|
/* V16QI tests. */
|
/* V16QI tests. */
|
|
|
void v16qi_vspltisb ()
|
void v16qi_vspltisb ()
|
{
|
{
|
v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
|
v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
|
vspltisb (w, 15);
|
vspltisb (w, 15);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisb_neg ()
|
void v16qi_vspltisb_neg ()
|
{
|
{
|
v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
|
v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
|
vspltisb (w, -5);
|
vspltisb (w, -5);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisb_addself ()
|
void v16qi_vspltisb_addself ()
|
{
|
{
|
v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
|
v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
|
vspltisb (w, 30);
|
vspltisb (w, 30);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisb_neg_addself ()
|
void v16qi_vspltisb_neg_addself ()
|
{
|
{
|
v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
|
v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
|
vspltisb (w, -24);
|
vspltisb (w, -24);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltish ()
|
void v16qi_vspltish ()
|
{
|
{
|
v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
|
v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
|
vspltish (w, 15);
|
vspltish (w, 15);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltish_addself ()
|
void v16qi_vspltish_addself ()
|
{
|
{
|
v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
|
v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
|
vspltish (w, 30);
|
vspltish (w, 30);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltish_neg ()
|
void v16qi_vspltish_neg ()
|
{
|
{
|
v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
|
v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
|
vspltish (w, -5);
|
vspltish (w, -5);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisw ()
|
void v16qi_vspltisw ()
|
{
|
{
|
v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
|
v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
|
vspltisw (w, 15);
|
vspltisw (w, 15);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisw_addself ()
|
void v16qi_vspltisw_addself ()
|
{
|
{
|
v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
|
v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
|
vspltisw (w, 30);
|
vspltisw (w, 30);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
void v16qi_vspltisw_neg ()
|
void v16qi_vspltisw_neg ()
|
{
|
{
|
v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
|
v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
|
vspltisw (w, -5);
|
vspltisw (w, -5);
|
check_v16qi (v, w);
|
check_v16qi (v, w);
|
}
|
}
|
|
|
|
|
/* V8HI tests. */
|
/* V8HI tests. */
|
|
|
void v8hi_vspltisb ()
|
void v8hi_vspltisb ()
|
{
|
{
|
v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
|
v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
|
vspltisb (w, 15);
|
vspltisb (w, 15);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltisb_addself ()
|
void v8hi_vspltisb_addself ()
|
{
|
{
|
v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
|
v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
|
vspltisb (w, 30);
|
vspltisb (w, 30);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltisb_neg ()
|
void v8hi_vspltisb_neg ()
|
{
|
{
|
v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
|
v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
|
vspltisb (w, -5);
|
vspltisb (w, -5);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltish ()
|
void v8hi_vspltish ()
|
{
|
{
|
v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
|
v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
|
vspltish (w, 15);
|
vspltish (w, 15);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltish_neg ()
|
void v8hi_vspltish_neg ()
|
{
|
{
|
v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
|
v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
|
vspltish (w, -5);
|
vspltish (w, -5);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltish_addself ()
|
void v8hi_vspltish_addself ()
|
{
|
{
|
v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
|
v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
|
vspltish (w, 30);
|
vspltish (w, 30);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltish_neg_addself ()
|
void v8hi_vspltish_neg_addself ()
|
{
|
{
|
v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
|
v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
|
vspltish (w, -24);
|
vspltish (w, -24);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltisw ()
|
void v8hi_vspltisw ()
|
{
|
{
|
v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
|
v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
|
vspltisw (w, 15);
|
vspltisw (w, 15);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltisw_addself ()
|
void v8hi_vspltisw_addself ()
|
{
|
{
|
v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
|
v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
|
vspltisw (w, 30);
|
vspltisw (w, 30);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
void v8hi_vspltisw_neg ()
|
void v8hi_vspltisw_neg ()
|
{
|
{
|
v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
|
v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
|
vspltisw (w, -5);
|
vspltisw (w, -5);
|
check_v8hi (v, w);
|
check_v8hi (v, w);
|
}
|
}
|
|
|
/* V4SI tests. */
|
/* V4SI tests. */
|
|
|
void v4si_vspltisb ()
|
void v4si_vspltisb ()
|
{
|
{
|
v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
|
v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
|
vspltisb (w, 15);
|
vspltisb (w, 15);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisb_addself ()
|
void v4si_vspltisb_addself ()
|
{
|
{
|
v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
|
v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
|
vspltisb (w, 30);
|
vspltisb (w, 30);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisb_neg ()
|
void v4si_vspltisb_neg ()
|
{
|
{
|
v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
|
v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
|
vspltisb (w, -5);
|
vspltisb (w, -5);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltish ()
|
void v4si_vspltish ()
|
{
|
{
|
v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
|
v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
|
vspltish (w, 15);
|
vspltish (w, 15);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltish_addself ()
|
void v4si_vspltish_addself ()
|
{
|
{
|
v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
|
v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
|
vspltish (w, 30);
|
vspltish (w, 30);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltish_neg ()
|
void v4si_vspltish_neg ()
|
{
|
{
|
v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
|
v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
|
vspltish (w, -5);
|
vspltish (w, -5);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisw ()
|
void v4si_vspltisw ()
|
{
|
{
|
v4si v = { 15, 15, 15, 15 };
|
v4si v = { 15, 15, 15, 15 };
|
vspltisw (w, 15);
|
vspltisw (w, 15);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisw_neg ()
|
void v4si_vspltisw_neg ()
|
{
|
{
|
v4si v = { -5, -5, -5, -5 };
|
v4si v = { -5, -5, -5, -5 };
|
vspltisw (w, -5);
|
vspltisw (w, -5);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisw_addself ()
|
void v4si_vspltisw_addself ()
|
{
|
{
|
v4si v = { 30, 30, 30, 30 };
|
v4si v = { 30, 30, 30, 30 };
|
vspltisw (w, 30);
|
vspltisw (w, 30);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
void v4si_vspltisw_neg_addself ()
|
void v4si_vspltisw_neg_addself ()
|
{
|
{
|
v4si v = { -24, -24, -24, -24 };
|
v4si v = { -24, -24, -24, -24 };
|
vspltisw (w, -24);
|
vspltisw (w, -24);
|
check_v4si (v, w);
|
check_v4si (v, w);
|
}
|
}
|
|
|
|
|
|
|
int main ()
|
int main ()
|
{
|
{
|
v16qi_vspltisb ();
|
v16qi_vspltisb ();
|
v16qi_vspltisb_neg ();
|
v16qi_vspltisb_neg ();
|
v16qi_vspltisb_addself ();
|
v16qi_vspltisb_addself ();
|
v16qi_vspltisb_neg_addself ();
|
v16qi_vspltisb_neg_addself ();
|
v16qi_vspltish ();
|
v16qi_vspltish ();
|
v16qi_vspltish_addself ();
|
v16qi_vspltish_addself ();
|
v16qi_vspltish_neg ();
|
v16qi_vspltish_neg ();
|
v16qi_vspltisw ();
|
v16qi_vspltisw ();
|
v16qi_vspltisw_addself ();
|
v16qi_vspltisw_addself ();
|
v16qi_vspltisw_neg ();
|
v16qi_vspltisw_neg ();
|
|
|
v8hi_vspltisb ();
|
v8hi_vspltisb ();
|
v8hi_vspltisb_addself ();
|
v8hi_vspltisb_addself ();
|
v8hi_vspltisb_neg ();
|
v8hi_vspltisb_neg ();
|
v8hi_vspltish ();
|
v8hi_vspltish ();
|
v8hi_vspltish_neg ();
|
v8hi_vspltish_neg ();
|
v8hi_vspltish_addself ();
|
v8hi_vspltish_addself ();
|
v8hi_vspltish_neg_addself ();
|
v8hi_vspltish_neg_addself ();
|
v8hi_vspltisw ();
|
v8hi_vspltisw ();
|
v8hi_vspltisw_addself ();
|
v8hi_vspltisw_addself ();
|
v8hi_vspltisw_neg ();
|
v8hi_vspltisw_neg ();
|
|
|
v4si_vspltisb ();
|
v4si_vspltisb ();
|
v4si_vspltisb_addself ();
|
v4si_vspltisb_addself ();
|
v4si_vspltisb_neg ();
|
v4si_vspltisb_neg ();
|
v4si_vspltish ();
|
v4si_vspltish ();
|
v4si_vspltish_addself ();
|
v4si_vspltish_addself ();
|
v4si_vspltish_neg ();
|
v4si_vspltish_neg ();
|
v4si_vspltisw ();
|
v4si_vspltisw ();
|
v4si_vspltisw_neg ();
|
v4si_vspltisw_neg ();
|
v4si_vspltisw_addself ();
|
v4si_vspltisw_addself ();
|
v4si_vspltisw_neg_addself ();
|
v4si_vspltisw_neg_addself ();
|
return 0;
|
return 0;
|
}
|
}
|
|
|