OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [pr26350.c] - Diff between revs 322 and 338

Only display areas with differences | Details | Blame | View Log

Rev 322 Rev 338
/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
/* { dg-options "-O2 -mlong-double-128 -fpic" } */
/* { dg-options "-O2 -mlong-double-128 -fpic" } */
 
 
typedef int int32_t __attribute__ ((__mode__ (__SI__)));
typedef int int32_t __attribute__ ((__mode__ (__SI__)));
typedef unsigned char uint8_t;
typedef unsigned char uint8_t;
typedef unsigned int uint32_t;
typedef unsigned int uint32_t;
typedef struct REGS REGS;
typedef struct REGS REGS;
typedef union { uint32_t F; } FW;
typedef union { uint32_t F; } FW;
typedef union { struct { FW L; } F; } DW;
typedef union { struct { FW L; } F; } DW;
typedef struct _PSW {
typedef struct _PSW {
  DW ia;
  DW ia;
} PSW;
} PSW;
struct REGS {
struct REGS {
  PSW psw;
  PSW psw;
  DW cr[16];
  DW cr[16];
};
};
struct ebfp {
struct ebfp {
  long double v;
  long double v;
};
};
 
 
void s390_convert_fix32_to_bfp_ext_reg (REGS *regs)
void s390_convert_fix32_to_bfp_ext_reg (REGS *regs)
{
{
  struct ebfp op1;
  struct ebfp op1;
  int32_t op2;
  int32_t op2;
  ((regs))->psw.ia.F.L.F += (4);
  ((regs))->psw.ia.F.L.F += (4);
  if(!((regs)->cr[(0)].F.L.F & 0x00040000))
  if(!((regs)->cr[(0)].F.L.F & 0x00040000))
    op1.v = (long double)op2;
    op1.v = (long double)op2;
  put_ebfp(&op1);
  put_ebfp(&op1);
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.